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Altera Triple-Speed Ethernet Timing Contraints Design Example

Altera Triple-Speed Ethernet Timing Contraints Design Example



Last Major Update

June 15, 2012 


Introduction

Altera Triple-Speed Ethernet Timing Contraints Design Example. This design example demonstrates how to use the Altera MegaWizard generated SDC file to constrain the Triple-Speed Ethernet IP core timing. This design example consists of the following verilog modules:

  1. TOP.v - Contains the top level PLL module and the user defined instance module. The top level input clock names are pll_clk, ext_clk and xcvr_ref_clk.
  2. user_instance.v – Contains the TSE core variation module that instantiates a 10/100/1000 Ethernet MAC, a MAC variation with internal FIFO buffers, with 1000BASE-X/SGMII PCS and embedded PMA. 
  3. tse_variation.v – Contains the TSE IP core module.


The frequency of the PLL inclk0 input and c0 output is 100MHz and 110MHz respectively. The PLL c0 output is used as the clock source for the FIFO data interface clocks, ff_tx_clk and ff_rx_clk. The frequency for the MAC control interface clock, clk, is 50MHz and it is sourced directly from the ext_clk signal. The frequency for the transceiver reference clock input is 125MHz.


Figure below shows the design block diagram of the Triple-Speed Ethernet timing contraints design example. 


f/f7/1.PNG


Timing Constraints

Steps to Constrain Timing Using MegaWizard Generated SDC File

    1. Set Clock Path

           (a) set CLK "ext_clk"

           (b) set REF_CLK "xcvr_ref_clk"

If you are using PLL-generated output clock as the clock source, obtain the PLL clock path from the TimeQuest timing analyzer clocks report, as shown in the figure below and set the clock name according to the PLL output clock path.

          (c) set FF_TX_CLK "altpll_tse_inst|altpll_component|auto_generated|pll1|clk[0]"

          (d) set FF_RX_CLK "altpll_tse_inst|altpll_component|auto_generated|pll1|clk[0]"

To avoid ignore create clock warnings in the TimeQuest timing analyzer report, you may comment out the unused clock names.


e/ed/2.PNG


    2.  Set Clock Frequency (you may comment out frequency parameters that are not applicable to your design)

              # Frequency of network-side interface clocks or reference clocks.

              set TSE_CLOCK_FREQUENCY "125 MHz"

              # Frequency of FIFO data interface clocks.

             set FIFO_CLOCK_FREQUENCY "110 MHz"

             # Frequency of MAC or PCS control and status interface clock.

             set DEFAULT_SYSTEM_CLOCK_SPEED "50 MHz"

    3. Constrain all PLL input and output clocks in the user design. This must be done external to the generated SDC file.

    4. Constrain reconfig_clk (if applicable) manually to avoid unconstrained clock warning in the TimeQuest timing analyzer. This must be done external to the generated SDC file.

    5. Repeat step 1 and step 2 if you re-generate the TSE IP core as the generated SDC file will replaced during IP re-generation.

Handnote: You need to constrain the reconfig_clk in the timing constraint file for MAC variation with embedded PMA block to avoid unconstrained clock warning in the TimeQuest timing analyzer.


SDC File Example

The following SDC file shows the user modifiable section of the timing constraint file based on design example described above.


Example 1-1. Timing Constraint SDC File


# Frequency of network-side interface clocks or reference clocks

# For MAC with PCS and PMA variant, this parameter applies to transceiver reference clock only.

set TSE_CLOCK_FREQUENCY "125 MHz"


# Frequency of FIFO data interface clocks

# This parameter is applicable to MAC variation with internal FIFO only

# For MAC variation without internal FIFO, user may comment out this parameter.

set FIFO_CLOCK_FREQUENCY "110 MHz"


# Frequency of MAC or PCS control and status interface clock

set DEFAULT_SYSTEM_CLOCK_SPEED "50 MHz"


# Name the clocks that will be coming into the tse core named changed from top level.

# TX_CLK, RX_CLK, TBI_TX_CLK and TBI_RX_CLK are not applicable to MAC with PCS and PMA variant.

# User may comment out the unused clock names.

#set TX_CLK "tx_clk"

#set RX_CLK "rx_clk"

#set TBI_TX_CLK "tbi_tx_clk"

#set TBI_RX_CLK "tbi_rx_clk"


#Set the CLK and REF_CLK parameters according to the top level pin names.

set CLK "ext_50M_clk"

set REF_CLK "xcvr_ref_clk"


# If you are using PLL generated output clock as the clock source, obtain the PLL clock path from the

# TimeQuest timing analyzer clocks report, as shown in the figure above.

# Set the clock name according to the PLL output clock path, as shown below.

set FF_TX_CLK "altpll_tse_inst|altpll_component|auto_generated|pll1|clk[0]"

set FF_RX_CLK "altpll_tse_inst|altpll_component|auto_generated|pll1|clk[0]"


# The following lines constrain the PLL input and output clocks.

# User is responsible for constraining the PLL inputs and outputs. Altera constraint file does not

# constrain PLL inputs and outputs in user design

# If the PLL inputs and outputs are not constrained elsewhere, and derive_pll_clocks is not applied, user

# will get the following Critical warnings:

# Critical Warning: Register-to-register paths between different clock domains is not recommended if

# one of the clocks is from GXB transmitter channel.

# Critical Warning: Register-to-register paths between different clock domains is not recommended if

# one of the clocks is from GXB receiver channel.

# This Critical Warning would be removed if PLL inputs and outputs clock are properly constrained.

# To avoid illegal clock warnings, the derive_pll_clocks command should not appear more than once in

# one or multiple SDC files for the same design.

Some humble thoughs from one user's perspective.

  • Unfortunately, one must install such modifications canonically each time that the QSYS system is regenerated, but its easy to neglect that task.
  • Unfortunately, the name CLK is quite generic and therefore a likely cause of name space colisions. Perhaps it would be better if the names included some of the subsystem path. This would also make the user's situation easier when ther are multiple MACs, and maybe it would also enable specifying the clock port in a top level SDC file.


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Download the design files used in this example:

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