Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your profile.
The following applies to designs with multiple Arria 10 External Memory Interface IPs (EMIF) in the same column of the Arria 10 device.
We will use an example of 3 Arria 10 EMIFs to show how to properly daisy-chain the cal_debug bus in Qsys which the EMIF Toolkit relies on to acquire calibration information
For simplicity, we have exported all EMIF ports that are unnecessary for calibration information
We must first setup EMIF A in the Diagnostics tab of the IP Parameter GUI
This will expose EMIF A's Avalon-MM Master calibration debug interface which we can connect to EMIF B's Avalon-MM Slave calibration debug interface
EMIF A's Diagnostics tab
Now must now setup EMIF B in the Diagnostics tab of the IP Parameter GUI
This will expose EMIF B's Avalon-MM Slave calibration debug interface which we can connect to EMIF A's Avalon-MM Master calibration debug interface
This will expose EMIF B's Avalon-MM Master calibration debug interface which we can connect to EMIF C's Avalon-MM Slave calibration debug interface
EMIF B's Diagnostics tab
Finally we setup EMIF C in the Diagnostics tab of the IP Parameter GUI
This will expose EMIF C's Avalon-MM Slave calibration debug interface which we can connect to EMIF B's Avalon-MM Master calibration debug interface
EMIF C's Diagnostics tab
We need to connect the following signals that make up the calibration debug interface to daisy-chain EMIF B to EMIF A
We need to connect the following signals that make up the calibration debug interface to daisy-chain EMIF C to EMIF B
EMIF B has both a slave calibration debug interface and a master calibration debug interface to connect to EMIF A and EMIF C respectively
Running Select Active Interface will allow you to switch between EMIFs when you wish to view useful calibration information about another EMIF
Select Active Interface will allow you to switch between EMIFs
Click here for a Qsys example to be used as reference only
The following applies to designs with multiple Arria 10 External Memory Interface IPs (EMIF) in the different column of the Arria 10 device.
Setting up EMIF interfaces in two different column are same when it comes to the Diagnostics tab of the IP Parameter GUI, unlike EMIF interfaces in same column
EMIF Diagnostics tab(both in this example)
Connect signals of both interface as shown in below diagram. You can treat both the interface signals as separate interface. No requirement of daisy-chain EMIF interfaces in this case
3/3c/Two_interface.JPG
Create Memory Interface Connection will allow you to switch between EMIFs.
In Toolkit Tasks window while creating a memory interface connection, you can select which memory IP you want to connect to. In below example, interface name Col2 belongs to EMIF IP in column 2 where as interface name col3 is EMIF IP in column 3. Once you establish initial connection for subsequent calibration run, you can select the interface from Task window and just rerun the calibration.
Select Memory Interface from drop-down menu.
Report window will show two different connections with separate reporting structure.
Calibration Report will show separate reports for each EMIFs.
This zip file contains three .qsys files. "two_interface.qsys" file is the final qsys file containing two EMIFs in different column. Once you open this qsys file, you will get an error in Quartus indicating that you can not elaborate this design. To remove the error, go to Tools->option in Qsys, and set the IP search path by adding the location for rest of the two qsys files. Once you added the path, you can find these two custom IP generation under Library->System in Qsys IP catalog window. Add this custom IP definition to you "two_interface.qsys". For signal connection to individual EMIFs in qsys, follow above screen capture.
Community support is provided Monday to Friday. Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.