Arria 10 EMIF Guidelines
Description
The following files assist users with the EMIF design process for Arria 10. Topics covered include: example design generation and simulation, timing closure considerations, fitter constraints, pin placement requirements, board design guidelines, and HPS EMIF.
Download Arria 10 EMIF Guidelines
Locate Example Design, Simulation, and Pin Guidelines under Device Selection and IP Generation > Generate EMIF IP
Locate HPS EMIF Design Guidelines under Device Selection and IP Generation > Additional Resources > HPS EMIF Guidelines
Locate Board Guidelines under Board Design and System-Level Timing Closure > Board Design > Board Design Guidelines
Locate Timing Closure Guidelines under Board Design and System-Level Timing Closure > Timing Check > Timing Closure Guidelines
