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Arria 10 EMIF Guidelines

Arria 10 EMIF Guidelines



Description

The following files assist users with the EMIF design process for Arria 10. Topics covered include: example design generation and simulation, timing closure considerations, fitter constraints, pin placement requirements, board design guidelines, and HPS EMIF.

Download Arria 10 EMIF Guidelines

Locate Example Design, Simulation, and Pin Guidelines under Device Selection and IP Generation > Generate EMIF IP

Locate HPS EMIF Design Guidelines under Device Selection and IP Generation > Additional Resources > HPS EMIF Guidelines

Locate Board Guidelines under Board Design and System-Level Timing Closure > Board Design > Board Design Guidelines

Locate Timing Closure Guidelines under Board Design and System-Level Timing Closure > Timing Check > Timing Closure Guidelines


Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 11:40 AM
Updated by:
 
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