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Arria 10 Hard Memory Controller DDR3 933MHz Quarter Rate x72 Dual Rank UDIMM

Design Example – Arria 10 Hard Memory Controller DDR3 933MHz Quarter Rate x72 Dual Rank UDIMM



Contents

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Last Major Update

Initial Release - December 2014 - Arria 10 Hard Memory Controller DDR3 933MHz Quarter Rate x72 Dual rank UDIMM, Quartus II v14.1, Arria 10 External Memory Interface.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 72-bit wide, 933-MHz DDR3 SDRAM hard memory interface working with a Arria 10 FPGA using a 72-bit wide DDR3 SDRAM interface accessing one MT18JSF1G72AZ-1G9 DDR3 SDRAM UDIMM module. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the Arria 10 External Memory Interface IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 2: Design Guidelines of the External Memory Interface Handbook should be used for a more thorough walkthrough.

To demonstrate the DDR3 SDRAM functionality, this lab will use the example design option provided in Arria 10 External Memory Interface IP. The synthesis example design will be later modified to add other components to demonstrate the flexibility of the example design to suite user needs.

Note that, all available Arria 10 devices including the target device for this lab are currently marked as either Advanced or Initial in Quartus II v14.1, thus no programming file will be generated. However, to ensure the steps are correct, similar design as in this lab has been created and verified through internal hardware testing. Thus, should the design need to be tested in different board (once the programming file support is available), the steps should remain the same but the design may require some modification (e.g. IP parameters and pin location assignment) and regeneration in latest Quartus release so that that it will match with the target board and to ensure it continue to work correctly.

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
Quartus version14.1
FPGA10AX115S3F45I2LG (Advanced)
Board / KitInternal Board
Memory deviceDDR3 SDRAM (Micron MT18JSF1G72AZ-1G9)
Memory speed933-MHz
Memory topologyx72-bit, 1 DDR3 SDRAM Dual rank UDIMM
IP usedArria 10 External Memory Interface
Simulator usedModelSim SE 10.3c

Lab Steps

The lab uses Quartus II v14.1 and has ModelSim set up for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

Three files have been pre-designed for this lab to save time:

1. A pin location assignments TCL script ( 10ax115s3f45i2lg_pin_assignment.tcl )

2. A custom Component Definition File of Example Design In-System Source and Probe ( ed_iss_hw.tcl )

3. A custom RTL wrapper for Example Design In-System Source and Probe ( ed_iss.v )

Files for this lab are located in this lab_files.tar.gz file.

Create a new folder for the project and place the files according to the instruction.

An archive for the final project is located in this a10egdesign.tar.gz file for reference.

Design Generation

1. In the Quartus II software, create a Quartus II project using the New Project Wizard available from the File menu. For this lab, use following information to setup the project accordingly: 

  • Working directory : < your project folder >
  • Project name : dut
  • Device name : 10AX115S3F45I2LG
  • Leave other settings to default

2. Launch the IP Catalog from the Tools menu

3. Double click Arria 10 External Memory Interfaces IP from the Memory Interfaces and Controllers folder in the Library list. IP Parameter Editor will be launch.

4. In New IP Variation window, specify the Entity name and click OK. For this lab, use following information to setup the IP variation accordingly. 

  • Entity name : dut
  • Leave other settings to default

5. In Presets window, select the preset matching or closest to the target memory device. For this lab, use ' DDR3-1866M CL13 UDIMM 1R x72 2GB (9 x256Mb x8) ' preset. Click Apply

Note : Based on MT18JSF1G72AZ-1G9 datasheet, we know that protocol is DDR3, the speed grade is -1G9, the Memory CAS latency (CL) is 13 and the data rate 1866 MT/s. Thus the closest preset is 'DDR3-1866M CL13 UDIMM 1R x72 2GB (9 x256Mb x8)'

6. Specify the parameters on all tabs. The value should be based on the target memory device, FPGA device and board being used. For this lab, use following information to configure the remaining IP parameter that should be different than the default value or the preset. 

  • I/O tab (Uncheck the Use default I/O settings checkbox) 
  • PHY Inputs 
  • PLL reference clock I/O standard = LVDS (Based on Arria 10 10AX115 Pin-out file)
  • Memory Topology tab 
  • Topology 
  • Number of clocks = 2 (Based on the MT18JSF1G72AZ-1G9 datasheet pg. 8)
  • Number of physical ranks per DIMM = 2 (Based on the MT18JSF1G72AZ-1G9 datasheet pg. 2)
  • Row address width = 16 (Based on the MT18JSF1G72AZ-1G9 datasheet pg. 2)
  • Memory Timing tab 
  • tRFC = 260 ns (Based on the MT41J512M8 - 107 datasheet pg. 81)
  • Board Timing tab (Based on internal board information) 
  • Slew Rates 
  • Use default slew rates = Unchecked
  • CK/CK# slew rate (Differential) = 4.0 V/ns
  • Address and command slew rate = 2.0 V/ns
  • Read DQS/DQS# slew rate (Differential) = 5.0 V/ns
  • Read DQ slew rate = 2.5 V/ns
  • Write DQS/DQS# slew rate (Differential) = 4.0 V/ns
  • Write DQ slew rate = 2.0 V/ns
  • Intersymbol Interference/Crosstalk 
  • Use default ISI/crosstalk values = Unchecked
  • Address and command ISI/crosstalk = 0.174 ns
  • Read DQS/DQS# ISI/crosstalk = 0.114 ns
  • Read DQ ISI/crosstalk = 0.133 ns
  • Write DQS/DQS# ISI/crosstalk = 0.051 ns
  • Write DQ ISI/crosstalk = 0.113 ns
  • Board and Package Skews 
  • Package deskewed with board layout (DQS group) = Unchecked
  • Maximum board skew within DQS group = 0.02 ns
  • Package deskewed with board layout (address/command bus) = Checked
  • Maximum system skew within address/command bus = 0.02 ns
  • Average delay difference between DQS and CK = 0.02 ns
  • Maximum delay difference between DIMMs/devices = 0.05 ns
  • Maximum skew between DQS groups = 0.02 ns
  • Average delay difference between address/command and CK = 0.0 ns
  • Maximum CK delay to DIMM/device = 0.6 ns
  • Maximum DQS delay to DIMM/device = 0.6 ns

Important Note : Review any warning messages displayed in the Messages Window and correct any errors before making further changes

Important Note : Instead of leaving it to default, ensure the parameters in Board Timing tab are configured correctly based on the actual target board as the value are vary from board to board. Use HyperLynx or similar simulator to obtain values of the actual target board.

Important Note : Take note on the info messages regarding which address/command pin placement scheme that need to follow based on the final IP setting. This info will be needed during pin assignment in the later stage.

Note : For Board and Package Skews, use Board Skew Parameter Tool available in Altera web to compute the value

Note : For detailed explanation of the parameters, refer to Parameterizing Memory Controllers with Arria 10 External Memory Interface IP chapter of the External Memory Interface Handbook.

7. Click Example Design button at the top-right corner of the Parameter window, confirm the default path for the example design, and click OK.

8. Once the generation completed, click Close.

9. Click Finish. The configuration is saved as dut.qsys which located inside < your project folder > directory.

10. Since this lab will only use the example design files, click No when prompted to generate your IP.

11. In Integration with the Quartus II Software window, click Close.

12. Click Yes when prompted to add the Quartus II IP File to the project.

13. In terminal, change directory to < your project folder >/emif_0_example_design folder and run following commands in sequence: 

i. $ quartus_sh -t make_qii_design.tcl

ii. $ quartus_sh -t make_sim_design.tc

Note : Review the readme.txt file generated under < your project folder >/emif_0_example_desig/qii/altera_emif_arch_nf_141/synth folder. The file contains high-level overview, recommendation and requirements of the IP based on the selected configuration.

Adding Components Into Existing Example Design (Optional)

1. Place the ed_iss.v and ed_iss_hw.tcl inside the < your project folder >/emif_0_example_design folder.

2. Launch the Qsys from the Tools menu.

3. In Open dialog box, navigate into < your project folder >/emif_0_example_design folder, select the ed_synth.qsys file and click Open.

4. Once the process of opening the system has been completed, click Close. An example design system containing the Arria 10 External memory Interface IP, EMIF example Avalon Traffic Generator and other miscellaneous blocks will appear in the System Contents window.

5. Since in this example we going to use the our own hw.tcl component, we need to add the path to the hw.tcl file so Qsys know where to find it. To do that click Tools > Option. Then, click the Add button and browse to the project folder where you place the ed_iss_hw.tcl before you click Finish.

6. In IP Catalog window, double click Example Design In-System Sources and Probes in the Library list to add the component into the system.

7. In Example Design In-System Sources and Probes GUI, click Finish. You can see in System Contents window a new component called ed_iss_0 is added.

8. Un-export the following signal by double click their corresponding export signal name in the Export column and delete the name. 

  • Component name : global_reset_splitter, Interface name : sig_input_if, Export name : global_reset
  • Component name : emif_0_example_design , Interface name : status_conduit_end, Export name : emif_0_example_design_status
  • Component name : tg , Interface name : tg_status_conduit_end, Export name : emif_0_example_design_tg_0

9. Make the following connection from ed_iss_0 interfaces 

  • reset_source to sig_input_if of global_reset_splitter
  • emif_status to status_conduit_end of emif_0_example_design
  • tg_status to tg_status_conduit_end of tg

10. Click Finish to save the system into the existing ed_syth.qsys file.

11. Click No when prompted with Generate Now?.

12. Click Yes when prompted to add the Quartus II IP File to the project.

13. In terminal, change directory to < your project folder >/emif_0_example_design folder and run following commands in sequence: 

i. $ rm -rf qii

ii. $ quartus_sh -t make_qii_design.tcl

Note : Alternative of using this custom component to add ISS is to add following Quartus II assignment in ed_synth.qpf file. This will enable the existing ISS that has been instantiated inside the IP RTL. 

  • set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1“

Design Constraint, Compilation And Analysis

1. In the Quartus II software, open the generated example design Quartus II project ( ed_synth.qpf) using the Open Project available from the File menu. The Quartus II project file should be under < your project folder >/emif_0_example_desig/qii folder.

2. Assign the location for all top level pins. Pin locations for external memory systems are not automatically created as it depend on the individual board layout and device package being used. For this lab, do the following steps: 

i. Place the 10ax115s3f45i2lg_pin_assignment.tcl in < your project folder >/emif_0_example_desig/qii.

ii. Launch the Tcl Scripts from Tools menu.

iii. In the TCL Scripts window, select the 10ax115s3f45i2lg_pin_assignment.tcl script under the Project folder in the Libraries and click Run to run the script.

iv. Click OK when a window appeared indicating the script has been executed and click Close to close the TCL Scripts window .

v. Verify in Pin Planner or Assignment Editor available under the Assignments menu to ensure the pin locations has been assigned correctly

Note : Board designer should comply with the following pin-out guideline when designing the board. To ensure the correctness, cross-check the pin location assignment with the respective document too. 

  • Guidelines for Arria 10 External Memory Interface IP topic under Planning Pin and FPGA Resources chapter of the External Memory Interface Handbook.
  • Pin locations section in the readme.txt file generated under < your project folder >/emif_0_example_desig/qii/altera_emif_arch_nf_141/synth folder
  • Arria 10 Device Pin-Out Files on Altera web. For this lab, refer to Pin List SF45 tab in 10AX115 Pin-Outs file.
  • Arria 10 External Memory Interface Pin Information on Altera web. Use the address/command pin placement scheme information (as in noted in Design Generation stage) to determine which column should be referred to.

3. Run full compilation by clicking the Start Compilation under the Processing menu. The compilation may take around 10 minutes to complete depending on compilation PC.

4. Once the compilation complete, ensure that there are no timing violation. There are 2 areas that should be check as below: 

  • In Messages window, ensure that "Critical Warning (332148): Timing requirements not met" message has not being printed out.
  • In Compilation Report window, in emif_0_example_design table under each TimeQuest Timing Analyzer / < Operating condition > / Report DDR folder, ensure all number are positive. Note that this report only cover for those that are under Arria 10 External Memory Interface IP clock domain.

5. Review all the Critical Warnings and Warnings and determines if it is acceptable or need to be address.

Design Hardware Test (Optional)

Important Note : All available Arria 10 devices including the target device for this lab are currently marked as either Advanced or Initial, thus no programming file will be generated. The following steps are just to demonstrate the various method to program and verify the design in the hardware which can be followed once the programming file support is available. For this lab to work, steps described under the Adding Components Into Existing Example Design topic is compulsory to be followed.

1. In the Quartus II software, launch In-System Sources and Probes Editor from Tools menu.

2. In Jtag Chain Configuration window under In-System Sources and Probes Editor GUI, configure the Hardware and Device based on the targeted board. For File, browse for the ed_synth.sof file and click Open.

3. Click Program Device button to configure the FPGA.

4. Once the configuration is successful (Ready to acquire), select all source and probe instances and click the Continuously Read Probe Data button next to Instance Manager label. The In-System Sources and Probes Editor Pane will shows the acquired data from each instances.

5. In In-System Sources and Probes Editor Pane, click the GRST or RSTN instance value under the Data column to change it from 0 to 1. This will de-assert the global_reset_n signal in the hardware.

6. Observe the data for CALS or CALP and TGP instances change from 0 to 1 which indicate the calibration is success and pass the example driver tests.

Design RTL Simulation

1. In terminal, change directory to < your project folder >/emif_0_example_design/sim/mentor folder and run following commands 

  • $ vsim -do 'source msim_setup.tcl ; dev_com ; com ; ld_debug ; add wave sim:/ed_sim/sim_checker/*pass_all ; add wave sim:/ed_sim/sim_checker/*any ; run -all'

2. ModelSim SE will be launched and the compilation and simulation will be run. The simulation may take around 60 minutes to complete depending on compilation PC.

3. Once the simulation stopped, observe the pass_all signal in waveform window to ensure it goes high and a " --- SIMULATION PASSED --- " string displayed in the ModelSim terminal to ensure the RTL simulation has passed.


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