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Arria 10 Power Sequencing using Enpirion and MAX10

Arria 10 Power Sequencing using Enpirion and MAX10

 

 

The latest generation of Altera and Xilinx FPGAs (Arria 10, Stratix 10, Ultrascale, Ultrascale+) have complex power requirements, in particular power supply sequencing order and timings.

This is a simple reference design for power sequencing an Arria 10 FPGA using Enpirion power products and a MAX10 FPGA; the design is deliberately basic so that end users can quickly understand and cut/paste into their own applications. The document also details modification ideas to upgrade the design for additional features.

The attached document details the design and how to use it. Also attached are two app notes from Diodes International on discharge considerations for FPGAs, plus the MAX10 design archive.

This is provided As Is, but we will try and answer any questions we can. Please forward any queries to either John Dillon - Power FAE (jdillon@altera.com) or Mark Frost - FAE (mfrost@altera.com)

[UPDATE MAY 2017] The Power Sequencer MAX10 design has been updated to fix a reset issue and to add debug functionality via the JTAG UART. The documentation is still broadly correct, but the sequencing start is now done via the JTAG UART rather than the DIP switches on the development board.

Simple Power Sequencer Design for MAX10 rev2.pdf

DMN3027LFG R0.pdf

DIAPR0232.pdf

PowerSequencing.zip

 

PowerSequencingMay2017_FixedReset.zip

 

 

Version history
Revision #:
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Last update:
‎03-08-2021 11:05 AM
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