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Arria 10 SerialLite II Design Example v19.1std

​This is the Arria 10 SerialLite II design example with 4 lanes at 10Gbps per lane using Arria 10 FPGA development kit (Production Edition). 

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v19_1std_sl2_design_example_a10.zip
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Last update:
‎10-31-2019 07:22 AM
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For more complete information about compiler optimizations, see our Optimization Notice.