This article lists the specifications and design zip files for Arria 10 Transceiver PHY design examples. The purpose of design examples is to assist the user with Arria 10 transceiver designs by giving a verified and easy to understand stand-alone design example. Each design example zip file has a user guide and necessary design files. The user guide helps to understand design example and provides instructions on how to simulate and compile.The design examples are available for Quartus v13.1a10 and for Quartus v14.0a10. Design examples for Quartus v14.0a10 are not backward compatible with Quartus v13.1a10 because of changes in Quartus Megawizard tool.
PIPE Design Example
PIPE design examples show implementation of Gen1 x4,Gen2 x8,Gen3 x1 and Gen3 x8 PIPE using Native PHY.
Transceiver Reconfiguration Design Example using Native PHY
There are two design examples demonstrating the Native PHY IP and PLL IP reconfiguration interfaces. The first design demonstrates how to switch between a 9.8Gbps ATX PLL to a 10.3Gbps ATX PLL. As part of this reconfiguration the channel CDRs are also reconfigured to support the new data rate. The second design demonstrates how to reconfigure a 8.5Gbps to a 10.3Gbps fPLL. As part of this reconfiguration the channel CDRs are also reconfigured to support the new data rate.
These design examples shows how to implement Tx skew reduction using six-channel bonded configuration, eighteen-channel bonded configuration. For six-channel bonded configuration x6 PMA bonding is used and for eighteen-channel configuration xN and Pll feedback compensation PMA Bonding are used.