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Arria 10 Voltage Sensor

Arria 10 Voltage Sensor



Download Source & Example Project

Example of .jam File for JTAG Access Mode http://www.alterawiki.com/wiki/File:ACT_VSSENSOR.zip>

Example project for Core Access Mode


Access the Voltage Sensor in JTAG Mode

The example .jam file is used to illustrate the flow in accessing the Voltage Sensor in JTAG Mode. 

The .jam file assumes there is only one Arria 10 device in the JTAG chain. It configures the voltage sensor and reads out the converted values.

  • For MD[1:0] not equal to 2’b11, the .jam file outputs the 16 converted values in the sequence sepecified by MD[1:0].For example, if MD[1:0]=2’b00, it outputs 16 converted values in the sequence of channel 2 to channel 7.
  • For MD[1:0]=2’b11, the .jam file outputs 15 converted values for the channel specified by MS[2:0]. 

We can increase the number of converted values by changing the "number_data" variable in line #22 of the .jam file.


Follow the steps below to run the ACT_VSSENSOR.jam file.

1)Modify ACT_VSSENSOR.jam file to configure the voltage sensor in other supported configurations.

Line #16 specifies the configuration register value and line #22 specifies the number of conversion data to be printed on screen.


5/50/Configuration_JTAG.PNG


Modify line #16 to change the configuration for the voltage sensor and line #22 to change the number of conversion data



























BOOLEAN D[12]=#010001000001; translates to the following configuration:

NAMS2MS1MS0NACALNANABU1BU0MD1MD0
010001000001

If you want to change MD[1:0]=2’b00 (i.e to sense voltage from channel 2 to channel 7) and BU1=1 (i.e to configure channel 1 in bipolar mode), you will need to change line #16 to the following:

BOOLEAN D[12]=#010001001000

Save the file after editing the .jam file.

2)Use quartus_jli command-line executable to run the “ACT_VSSENSOR.jam”. At command prompt:

a)Change to directory where the jam file is located.

b)Type <quartus_installation_path>\quartus\bin64\quartus_jli -a ACT_VSSENSOR ACT_VSSENSOR.jam


Output After Running "ACT_VSSENSOR.jam"

1)MD[1:0]=00

b/bc/MD00.png

MD[1:0]=2'b00

3/3d/MD11_CH100.png





























2)MD[1:0]=2'b11, MS[2:0]=3'b100



MD[1:0]=2'b11































Access the Voltage Sensor in Core Access Mode

The example designs target the Arria 10 GX FPGA Development Kit.The example design consists of the following instances:

a)In-sytem Sources and Probes to assert/de-assert user reset

b)IOPLL to synthesize a 20MHz clock for the voltage sensor and user logic

c)Voltage Sensor WYSIWYG atom (twentynm_vsblock)

d)User logic to configure the voltage sensor(Example_SM)

e)User logic to latch the converted data and keep track of the converted channel(Data_process)


To run the example design: 

1)Compile the design

2)Program the device with the sof file

3)In the SignalTapII file, trigger on the falling edge of Example_SM:sm_inst|reset_in signal as shown in the picture below:


8/8b/Triggering_MD01.png

SignalTap II Trigger Condition
























4)Use In-sytem Sources and Probes Editor to assign source[1:0]=2'10 to configure the Voltage Sensor


2/27/ISSP.png

In-sytem Sources and Probes Editor












5)Observe the SignalTapII result

Output signals from the voltage sensor block:

  • dataout_wire_vs[11..0]
  • eoc_wire_vs
  • eos_wire_vs

Output signals from user logic:

  • process_inst|logical_channel[3..0] ==>User can keep track the data_latched belongs to which channel
  • process_inst|data_latched[11..0]==>Data latched after the falling edge of eoc
  • process_inst|conversion_cycle[15..0]
  • process_inst|data_valid



SignalTap II result for MD[1:0]=2'b01(channel sequencer cycles from channel 0 to channel 7), BU[1:0]=2'b00 (Unipolar Mode)


0/06/STP_Core_MD01.png

External channels(CH=0 and CH=1) are tied to GND on Arria 10 GX FPGA Development Kit


















SignalTap II result for MD[1:0]=2'b11(user controls which channel to be converted), BU[1:0]=2'b01 (Ch1=Uniploar Ch0=Bipolar)


b/b2/STP_Core_MD11.png

User cycles from Ch4 ==> CH2 ==> Ch1 ==> Ch3. Data on chsel[3:0] needs to be ready one clock cycle before coreconfig de-asserts or eoc asserts
















To change the example design to configure the voltage sensor in other configurations for MD[1:0] not equal to 2'b11

1)Example_SM.v : Edit line #28 to line #35 to the new configuration register setting

a/ad/Core_MD01_SM.PNG


The parameters are self-explanatory




























2)Data_process.v: Edit line #29 and #30 according to MD[1:0] setting that you have changed in step (1) above. Follow the comments provided in the file.

9/9b/Core_MD01_Data_process.png


Edit FIRST_CHANNEL & LAST_CHANNEL parameters based on MD[1:0] setting
























To change the example design to configure the voltage sensor in other configurations for MD[1:0]= 2'b11

1)Example_SM.v : Edit line# 36 to line# 50 to the new configuration register setting.

c/c2/Core_MD11_SM.png


  • number of channels =4 as user cycles from Ch4 ==> CH2 ==> Ch1 ==> Ch3. LAST_CHSEL_SELECT= 3























2)MUX.v: Edit the channel(s) that you want to convert. It cycles in the sequence of a,b,c,d,e,f,g,h. The last channel is determined by the LAST_CHSEL_SEL parameter specified in Example_SM.v. This example design only cycles through a,b,c,d and repeats the same sequence again as LAST_CHSEL_SEL=3.

  • If you want to convert only channel 3, set LAST_CHSEL_SEL=0 and a=4'b0011.



Edit parameter a,b,c,d,e,f,g,h to the sequence you want




















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Last update:
‎06-21-2019 08:46 PM
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