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Arria V LVDS Basic Design Examples

Arria V LVDS Basic Design Examples

 

Arria V LVDS in DPA mode design example

Overview

This basic design example demonstrates the implementation of Arria V LVDS in DPA mode. With DPA mode enabled, the DPA block will help to choose the best possible sampling clock from the eight sampling clock sent from fractional PLL (fPLL). This would improve the receiver channel's jitter tolerance and ability to sample the incoming data correctly. In this design, In-System Source and Probe (ISSP) is used to control the resets, RX bit slip and DPA hold signals. Plug in the HSMC loopback board onto the Arria V starter kit to loopback the data from TX to RX. Then compile the design and program the device. Open up the stp1.stp SignalTap file and link to the Arria V device. You should observe the tx_locked, rx_locked and rx_dpa_locked are asserted. The rx_out might have incorrect word boundary after power up. Launch the In-System Source and Probe instance at Project Navigator -> Files -> Spf2.spf. You may apply RX bit slip by controlling the source[1] in the ISSP to achieve the right word boundary.

Design File

Arria V LVDS in DPA mode design example QII v13.1 (QAR)     

Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device ArriaV GX
Quartus version QuartusII v13.1
Development Kits Altera Arria V Starter Kit
Data rate 600Mbps
Data pattern Fixed
Number of channels 1
IP used ALTLVDS_TX, ALTLVDS_RX

Arria V LVDS with DPA in soft-CDR mode design example

Overview

This basic design example demonstrates the implementation of Arria V LVDS with DPA in soft-CDR mode. By having the soft-CDR mode in place, only the serial data is sent from the transmitter (TX) to the receiver (RX). The RX will be able to recover the sampling clock from the serial data received. This will help to save the board resource on the clock routing.

In this design, In-System Source and Probe (ISSP) is used to control the resets, RX bit slip and DPA hold signals. Plug in the HSMC loopback board onto the Arria V starter kit to loopback the data from TX to RX. Then compile the design and program the device. By default, you should observe that the RX DPA hold signal is asserted. Since the TX and RX are driven by different on-board oscillators, there is a ppm difference between the TX and RX. With the DPA tracking held, you should observe the RX parallel data output drifts. Launch the In-System Source and Probe instance at Project Navigator -> Files -> Spf2.spf. Write a value of '1' to the source[2] to release the DPA hold and allow the DPA to track the incoming serial data. You should now observe the RX parallel data output remain stable. You may then apply RX bit slip by controlling the source[1] in the ISSP to achieve the right word boundary.

Design File

Arria V LVDS with DPA in soft-CDR mode design example QII v13.1 (QAR)     

Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device ArriaV GX
Quartus version QuartusII v13.1
Development Kits Altera Arria V Starter Kit
Data rate 500Mbps
Data pattern Fixed
Number of channels 1
IP used ALTLVDS_TX, ALTLVDS_RX

 

Version history
Revision #:
3 of 3
Last update:
‎03-16-2021 02:03 PM
Updated by: