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Arria V Power

Arria V Power



The Arria V FPGAs offer an optimized balance between power, performance and price. The 28LP process provides the ability to have the lowest static power for midrange FPGAs and the architecture has been tailored to maintain your current performance while giving you a huge power savings.

How Low Can You Go with Arria V Contest- Entering is as easy as 1-2-3

Step 1:

Get the  Arria V PowerPlay Early Power Estimator 

Step 2:

Model your design using the EPE

Step 3:

Submit your design to be entered into the  drawing and enter to win a grand prize of an Arria V FPGA Development Kit!

Click here to email your design to Altera

Calculating power consumption can be done in two ways, the first with the PowerPlay Early Power Estimator spreadsheet tool, the second within Quartus II.

  • The Early Power Estimator takes in your design resource counts, but also the system conditions, such as operating temperature, junction temperature, heatsink type, airflow, and PCB types to most accurately model your power consumption. The tool will output not only the total power, but also the power consumed by each set of elements in the FPGA, the static power, current consumed by each power rail, the junction temperature, and the theta JA, representing the thermal efficiency of the FPGA.
  • Quartus II will also evaluate your power consumption at a higher accuracy as it takes into account your exact design and the actual resource count and switching of each register in your design. Furthermore, you can generate an Early Power Estimator from Quartus II for any existing design and import it into another Early Power Estimator, either for the same device, or for a different target device.


Benchmarks against Xilinx’s Series 7 FPGAs shows Arria V FPGAs consume significantly lower total, static and transceiver power. Get details on the actual design along with the actual Early Power Estimator spreadsheets to get the details of this benchmarking.


Version history
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Last update:
‎06-21-2019 08:52 PM
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