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Arria V Transceiver PHY Basic Design Examples

Arria V Transceiver PHY Basic Design Examples



Overview

Arria V Native PHY with manual alignment, 8b10b enabled and 20 bit PCS-PMA width design example

This basic design example with Modelsim simulation demonstrates the implementing of Arria V Native PHY with manual alignment, 8b10b enabled and 20 bit PCS-PMA. The purpose of this design example is to assist users to have quick start with the Arria V transceivers. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The design consist of only one transceiver channel with fixed 16 bits data pattern. Note that you should create your word alignment controller as the controls are done in test bench in the example.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Arria V Native PHY with manual alignment, 8b10b enabled and 20 bit PCS-PMA width design example QII ...    

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceArria V GX
Quartus versionQuartusII v15.0.2
Modelsim versionModelSim ALTERA STARTER EDITION 10.3d
Datarate3.2Gbps
Data patternFixed
Number of channels1
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller

Arria V Native PHY with manual alignment and data rate change with TX local divider dynamic reconfiguration design example in Quartus Prime 15.1

Overview

This basic design example with Modelsim simulation demonstrates the implementing of Arria V Native PHY with manual alignment and data rate change with TX local divider dynamic reconfiguration in Quartus Prime 15.1. The purpose of this design example is to assist users to have quick start with the Arria V transceivers TX local divider dynamic reconfiguration using MIF mode as well as manual alignment. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The design show reconfiguration from 800Mbps to 1600Mbps after achieving synchronization. There is no TX PLL reconfiguration required in this case. Note that you should create your dynamic reconfiguration state machine as the controls are done in test bench in the example.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Arria V Native PHY with data rate change using TX PLL switching dynamic reconfiguration design examp...

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceArria V GX
Quartus versionQuartus Prime v15.1
Modelsim versionModelSim ALTERA STARTER EDITION 10.4b
Datarate800Mbps and 1600Mbps
Data patternFixed and incremental
Number of channels1
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller

Arria V Custom PHY simple ways to enable internal serial loopback design examples

Overview

These basic design examples demonstrates simple ways to enable internal serial loopback in Arria V Custom PHY to facilitate issue debugging. By having the serial loopback in place, it allows you to focus on the transceiver blocks debugging and get away from external factors ie signal integrity. There are two design examples attached - one is with auto internal serial loopback enabled and another is manual enabled through In-System Source and Probe (ISSP). The designs have been tested with Arria V Starter kit.

For the auto enabled design example, once the receiver's rx_is_lockedtoref signal goes high, the serial loopback will be enabled. As for the manual enabled design example, after downloading the SOF file, you will need to launch the In-System Source and Probe Editor at the Quartus II -> Tools menu. Write a value of '1' to the source[1] in the ISSP Editor to enable the internal serial loopback. Note that these designs should serve as a quick reference to enable serial loopback. You should code your own control logics to enable the serial loopback.

Design File

Arria V Custom PHY simple way to auto enable serial loopback design example QII v13.1 (QAR) 


Arria V Custom PHY simple way to manually enable serial

loopback with ISSP design example QII v13.1 (QAR)    

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceArria V GX
Quartus versionQuartusII v13.1
Datarate1.25Gbps
Data patternFixed
Number of channels1
IP usedCustom PHY IP, Transceiver PHY Reconfiguration Controller

Arria V Native PHY with data rate change using TX PLL switching dynamic reconfiguration design example in Quartus Prime 15.1

Overview

This basic design example with Modelsim simulation demonstrates the implemention of Arria V Native PHY with data rate change using TX PLL switching dynamic reconfiguration in Quartus Prime 15.1. The two TX PLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Arria V transceivers TX PLL switching using MIF mode reconfiguration. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The design show reconfiguration from 1.0Gbps to 1.5Gbps after achieving synchronization. Note that you should create your dynamic reconfiguration state machine as the controls are done in test bench in the example.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Arria V Native PHY with data rate change using TX PLL switching dynamic reconfiguration design examp...)     

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceArria V GX
Quartus versionQuartus Prime v15.1
Modelsim versionModelSim ALTERA STARTER EDITION 10.4b
Datarate1.0Gbps and 1.5Gbps
Data patternFixed and incremental
Number of channels1
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller


Version history
Revision #:
1 of 1
Last update:
‎06-21-2019 08:53 PM
Updated by:
 
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