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Autonomous HIP and CvP Example Designs for Arria V GT FPGA Development Kit

Autonomous HIP and CvP Example Designs for Arria V GT FPGA Development Kit

(Redirected from Arria V Autonomous HIP and CvP Example Designs)



Description

These are example designs of Autonomous HIP and CvP for Arria V GT FPGA Development Kit based on PCI Express Avalon-ST High-Performance Reference Design



  • FPGA Designs
  • PCIe Gen1 x1 Avalon-ST64bit Autonomous mode
  • PCIe Gen1 x1 Avalon-ST64bit CvP Initialization mode
  • PCIe Gen1 x1 Avalon-ST64bit CvP Initialization and Update mode
  • PCIe Gen1 x1 Avalon-ST64bit CvP Update mode
  • PCIe Gen2 x4 Avalon-ST128bit Autonomous mode
  • PCIe Gen2 x4 Avalon-ST128bit CvP Initialization mode

The configuration scheme is FPPx16.

These designs include Conversion Setup File (.cof) and tcl file for Convert Programming Files during full compilation. 


  • MAX II System Controller

Following items were changed:

  • Added Flash Programming feature
  • CONF_DONE LED blinks when INIT_DONE
  • FPGA A LED turns on and off according to CVP_CONFDONE status


  • Hardware Setup
  • Set factory Default except for SW5.3
  • Set SW5.3 to "Off" to load user design
  • Program MAXII with attached MAXII design POF


Content


Version history
Revision #:
1 of 1
Last update:
‎06-21-2019 08:51 PM
Updated by:
 
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