Overview
The Avalon MicroSequencer works by stepping through 36-bit microcode stored in internal synchronous ROM implemented using Stratix®, Cyclone®, or Cyclone II embedded RAM blocks. The 36-bit instruction word consists of a 4-bit opcode and a 32-bit immediate data field. The size of the instruction ROM is configurable (up to 64K of instruction words) in the component’s SOPC Builder Wizard.
Figure 1. Block Diagram- Avalon-block.gif (Click here for image)
The system requirements to use the Avalon MicroSequencer Reference Design include:
You are free to use this design in any way you like. If you want to contibute to this project feel free to do so. I'm providing this design as is and Altera will not be supporting it. An alternative to this design is to use the Nios II 'e' core. Beginning in the Quartus Design Suite version 9.1 you can use the Nios II 'e' core without the need to purchase a license to use it.
Download File:Avalon uSequencer.zip
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