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Avalon MicroSequencer

Avalon MicroSequencer

The Altera® Avalon® MicroSequencer is a high-speed, low logic element (LE)-usage Avalon master with 32-bit data and address buses that employs a minimal instruction set to perform Avalon bus transfers as well as simple calculations. It can be used to control, initialize, and service peripherals in an Avalon system in applications that require extremely deterministic behavior. The Avalon MicroSequencer provides a solution where less logic and functionality than a microprocessor is required, as well as in time-critical designs where engineering a custom state machine would excessively increase time-to-market.


The Avalon MicroSequencer works by stepping through 36-bit microcode stored in internal synchronous ROM implemented using Stratix®, Cyclone®, or Cyclone II embedded RAM blocks. The 36-bit instruction word consists of a 4-bit opcode and a 32-bit immediate data field. The size of the instruction ROM is configurable (up to 64K of instruction words) in the component’s SOPC Builder Wizard.


  • Supports 16 instructions with 32-bit data field
  • Small size 135 LEs or 270 LEs
  • Configurable with or without an accumulator

Demonstrated Altera Technology

Block Diagram

Figure 1. Block Diagram- Avalon-block.gif (Click here for image)


System Requirements

The system requirements to use the Avalon MicroSequencer Reference Design include:

  • Quartus® II Software Version 7.0 or
  • Quartus II Software Version 7.1 and later using SOPC Builder in Classic Mode


You are free to use this design in any way you like. If you want to contibute to this project feel free to do so. I'm providing this design as is and Altera will not be supporting it. An alternative to this design is to use the Nios II 'e' core. Beginning in the Quartus Design Suite version 9.1 you can use the Nios II 'e' core without the need to purchase a license to use it.

Download  File:Avalon

Version history
Last update:
‎06-27-2019 12:10 AM
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