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Avalon-ST Protocol Analyzer

Avalon-ST Protocol Analyzer


Introduction

This Wiki page describes a systemverilog module which logs the Avalon-ST transactions to a log and PCAP(Packet Capture) file for easier debug. The module can be instantiated using QSYS or as a traditional systemverilog module.

A filename for the LOG and PCAP files can be set when instantiating the module. If the filename is left blank it will create a filename based on the design hierarchy which will be unique.

PCAP files can be displayed and decoded using the viewer from Wireshark www.wireshark.org. The PCAP file format is specified in wiki.wireshark.org/Development/LibpcapFileFormat.

Design Files

Download the following ZIP file for design files. File:Avalon st protocol analyzer.zip

Filename in zipDescription
avalon_st_protocol_analyzer_hw.tclQSYS Component file.
avalon_st_protocol_analyzer.svTop systemverilog module.
avalon_st_protocol_analyzer_core.svCore module doing actual logging.

Module Declaration

module avalon_st_protocol_analyzer #(

parameter LOG_FILENAME = ""

,parameter PCAP_FILENAME = ""

,parameter USE_PACKET = 1

,parameter USE_CHANNEL = 1

,parameter USE_ERROR = 1

,parameter USE_READY = 1

,parameter USE_VALID = 1

,parameter USE_EMPTY = 1

,parameter ST_SYMBOL_W = 8

,parameter ST_NUMSYMBOLS = 8

,parameter ST_CHANNEL_W = 0

,parameter ST_ERROR_W = 0

,parameter ST_EMPTY_W = 3

,parameter ST_READY_LATENCY = 0

,parameter ST_MAX_CHANNELS = 0

,parameter ST_BEATSPERCYCLE = 1

// Derived Parameters

,parameter ST_BPC = ST_BEATSPERCYCLE

,parameter ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS

) (

input wire clk

,input wire reset

,output logic sink_ready

,input wire [lindex(ST_BPC) :0] sink_valid

,input wire [lindex(ST_BPC*ST_CHANNEL_W):0] sink_channel

,input wire [lindex(ST_BPC) :0] sink_startofpacket

,input wire [lindex(ST_BPC) :0] sink_endofpacket

,input wire [lindex(ST_BPC*ST_EMPTY_W) :0] sink_empty

,input wire [lindex(ST_BPC*ST_DATA_W) :0] sink_data

,input wire [lindex(ST_BPC*ST_ERROR_W) :0] sink_error

,input wire src_ready

,output logic [lindex(ST_BPC) :0] src_valid

,output logic [lindex(ST_BPC*ST_CHANNEL_W):0] src_channel

,output logic [lindex(ST_BPC) :0] src_startofpacket

,output logic [lindex(ST_BPC) :0] src_endofpacket

,output logic [lindex(ST_BPC*ST_EMPTY_W) :0] src_empty

,output logic [lindex(ST_BPC*ST_DATA_W) :0] src_data

,output logic [lindex(ST_BPC*ST_ERROR_W) :0] src_error

);

Using the module in QSYS

The _hw.tcl file is the QSYS component declaration for the "Avalon-ST Protocol Analyzer" component. In order for the QSYS tool to see the component you must first add the directory to it's IP Search Path. In Qsys goto "Tools" followed by "options". Click on the "IP Search Path" category and add the directory where the _hw.tcl file is stored.

Now the component is available on in the Library. It can now be found under the "Avalon Verification Suite", "Altera Avalon-ST Protocol Analyzer".

LOG File Example

PCAP File Example

Multichannel Capture in Wireshark

The PCAP file format does not allow for any channel information to be stored. To work around this I've used the ts_sec (timestamp seconds) field to indicated the channel number. In order for the frames to be displayed correctly you must configure time display format in wireshark as shown in the picture below.

Summary

Attachments
Version history
Revision #:
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Last update:
‎06-21-2019 09:17 PM
Updated by:
 
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