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BittWare ATLANTiS FrameWork (AFW) FPGA Development Kit for BittWare

BittWare ATLANTiS FrameWork (AFW) FPGA Development Kit for BittWare’s Altera FPGA Boards

BittWare ATLANTiS FrameWork (AFW) FPGA Development Kit for BittWare’s Altera FPGA Boards

ATLANTiS FrameWork (AFW) provides FPGA board support IP and integration for BittWare’s Altera FPGA-based COTS boards. A library of FPGA components that includes preconfigured physical interfaces, infrastructure, and examples, AFW drastically cuts development time and can be easily integrated into existing FPGA development environments. Working example projects for each supported board, which illustrate how to move data between the board’s different interfaces, along with full simulation and synthesis example projects allow customers to have a board up and running within hours. AFW includes all source code and is provided with our BittWorks II Toolkit.

AFW includes all the physical interface components necessary for providing board-specific external I/O interfaces. In a typical FPGA design, physical interface development can account for the majority of the development time, but using AFW’s pre-configured physical interface components saves months of design effort. The physical interfaces are verified and performance tested and have been configured to meet the specific requirements of each BittWare FPGA-based board. Many of the AFW physical interfaces are Altera IP cores with a component wrapper to configure them for the BittWare board, ensuring that the IP is optimized for both the FPGA and the board.

To help further reduce integration time, AFW includes a library of optional components for system, interconnect, and simulation and test. Each component in AFW uses a standard API for communication: the Altera Avalon Streaming and Memory Mapped interfaces. By using a common interface, components become more reusable and portable.

AFW includes board-level projects to define all board-specific details for each supported product. These scripts define the resources available to the FPGA for each board, including I/O constraints, device-specific configuration, pin locations, and voltage levels.


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Last update:
‎06-24-2019 05:27 PM
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