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BluePrint Platform Designer Synthesizable Example Projects

Interface Planner (BluePrint Platform Designer) Synthesizable Example Projects

This wiki page has been created so that Quartus Interface Planner (formerly BluePrint Platform Designer) users can use some example templates to begin their planning. The designs uploaded to this page complete the synthesis process allowing a user to go into BluePrint and verify their pinouts match the device selected very early in their design.

Two approaches can be used to bring in the BluePrint pinout locations into your design.

1. Export the pin constraints to a tcl file, bring up Quartus, and source the tcl file which will add all the constraints into the qsf file. This makes the qsf file very large in some cases.

2. Export the pin constraints to a tcl file, remove all lines from the beginning of the tcl file to and including the line that says "remove_all_instance_assignments -name LOCATION". Then, remove the last line "export_assignments" from the tcl file and save. In the qsf file, add the line "source <filename>.tcl" where <filename> is the name you gave the tcl file exported from BluePrint.

Most designs will contain black boxes that are setup as partitions set to "empty". The user side application connections or other non-pin related connections were brought to a black box setup as an empty partition so that the IP would not be synthesized away.

Arria 10 Example designs by family

A10_SX_16.0_4DDR3x24_HPSDDR3x16_MISC_IO

  • This design has been synthesized in 16.0 to an Arria 10 10AS066K5F40I3SG device.
  • The design contains four, 24 bit wide DDR3s and an ARM HPS system with associated 16 bit wide DDR3.
  • The design was also run through the partition merge phase
  • Quartus was closed and then BluePrint was opened.
  • BluePrint was used to assign the IO and verified as legal.
  • The BluePrint constraints were then exported as a tcl file.
  • The tcl file was copied and edited to remove the header and last line then qsf file was changed to add a line to source the tcl file.
  • The design was then opened compiled.
  • A user can comment out the source pin assignments line in the qsf file, synthesize, then enter BluePrint to pin plan.
  • This design has some miscellaneous I/O with associated voltage standards. This is a good way to make sure that the device has all the necessary bank VCCIO requirements to fit all pins in the design.

A10 SX 16.0 4DDR3x24 HPSDDR3x16 MISC IO.qar - See attached at the bottom of this article

A10_SX_16.0_2DDR3x72_HPSDDR3x40

  • This design has been synthesized in 16.0 to an Arria 10 10AS066K2F40I2SG device.
  • The design contains two, 72 bit wide DDR3s and an ARM HPS system with associated 40 bit wide DDR3.
  • The design was also run through the partition merge phase
  • Quartus was closed and then BluePrint was opened.
  • BluePrint was used to assign the IO and verified as legal.
  • The BluePrint constraints were then exported as a tcl file.
  • Quartus was then re-opened and the tcl file was run which adds all the pin constraints to the qsf file.
  • The design was then opened and compiled.
  • A user can comment out the source pin assignments line in the qsf file, synthesize, then enter BluePrint to pin plan.

A10 SX 16.0 2DDR3x72 HPSDDR3x40.qar - See attached at the bottom of this article

A10_SX_16.0_4DDR4x16_PCIe_gen3x8

  • This design has been synthesized in 16.0 to an Arria 10 10AX048H2F34I1SG device.
  • The design uses a GX device and not an SX device as the name and associated RTL files might suggest.
  • The design contains four, 16 bit wide DDR4s and a PCIe Gen 3x8 interface.
  • The design was also run through the partition merge phase
  • Quartus was closed and then BluePrint was opened.
  • BluePrint was used to assign the IO and verified as legal.
  • The BluePrint constraints were then exported as a tcl file.
  • The tcl file was copied and edited to remove the header and last line then qsf file was changed to add a line to source the tcl file.
  • The design was then opened compiled.
  • A user can comment out the source pin assignments line in the qsf file, synthesize, then enter BluePrint to pin plan.

A10 SX 16.0 4DDR4x16 PCIe gen3x8.qar - See attached at the bottom of this article

A10_GX_16.0_8DDR4x16_48XCVR

  • This design has been synthesized in 16.0 to an Arria 10 10AX115N1F45I1SG device
  • The design contains eight, 16 bit wide DDR4s and 48 transceivers.
  • The design was also run through the partition merge phase
  • Quartus was closed and then BluePrint was opened.
  • BluePrint was used to assign the IO and verified as legal.
  • The BluePrint constraints were then exported as a tcl file.
  • The tcl file was copied and edited to remove the header and last line then qsf file was changed to add a line to source the tcl file.
  • The design was then opened compiled.
  • A user can comment out the source pin assignments line in the qsf file, synthesize, then enter BluePrint to pin plan.

A10 GX 16.0 8DDR4x16 48XCVR.qar - See attached at the bottom of this article

A10_GX_16.0_4DDR4x64_UDIMM

  • This design has been synthesized in 16.0 to an Arria 10 10AX115N2F45E1SG device
  • The design contains four, 64 bit wide DDR4s.
  • The design was also run through the partition merge phase
  • Quartus was closed and then BluePrint was opened.
  • BluePrint was used to assign the IO and verified as legal.
  • The BluePrint constraints were then exported as a tcl file.
  • The tcl file was copied and edited to remove the header and last line then qsf file was changed to add a line to source the tcl file.
  • The design was then opened compiled.
  • A user can comment out the source pin assignments line in the qsf file, synthesize, then enter BluePrint to pin plan.

A10 GX 16.0 4DDR4x64 UDIMM.qar - See attached at the bottom of this article

A10_GX_16.0_16DDR4x8

  • This design has been synthesized in 16.0 to an Arria 10 10AX115N2F45I2SGE2 device
  • The design contains four, 64 bit wide DDR4s.
  • The design was also run through the partition merge phase
  • Quartus was closed and then BluePrint was opened.
  • BluePrint was used to assign the IO and verified as legal.
  • The BluePrint constraints were then exported as a tcl file.
  • The tcl file was copied and edited to remove the header and last line then qsf file was changed to add a line to source the tcl file.
  • The design was then opened compiled.
  • A user can comment out the source pin assignments line in the qsf file, synthesize, then enter BluePrint to pin plan.

A10 GX 16.0 16DDR4x8.qar - See attached at the bottom of this article

External Links

  1. Interface Planner
  2. Quartus Prime Software Overview

 

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Last update:
‎07-13-2020 01:03 PM
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