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Booting Nios from Serial Flash with the new Altera Serial Flash Controller

Booting Nios from Serial Flash with the new Altera Serial Flash Controller


The information on the page had been superseded by the information in the new AN 736: Nios II Processor Booting From Altera Serial Flash.

This app. note can be downloaded at the following URL:

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an736.pdf


Saved for reference only...

In Quartus 14.1, Altera introduced a new serial flash loader which can be used to program and load serial and quad SPI flash devices. Here is how to properly program your Nios II executable into a serial flash so that your Nios can boot from the flash. This implementation assumes that the serial flash is simply storage and that the executable will be loaded into and executed from RAM. This has been verified with an EPCS16 serial flash.

This example uses the Quartus Programmer, not the nios2-flash-programmer (only because that was the flow I needed to use when I did this.)

This example uses the CFI flash bootloader and eliminates some of the problems with the programming and boot flow of the old EPCS Flash controller.

An example project containing both Quartus and Nios II SW projects can be downloaded here: File:Epcq test be micro sdk.zip. This example targets the BeMicroSDK board.

This example uses the Quartus II programmer for programming the EPCS, not the Nios II Flash Programmer, as that is what was required for this specific project.

Creating your HW Design:


  • In your Nios QSys system, instantiate and configure the Altera Serial Flash Controller
  • In the Nios II Configuration GUI, go to the Reset vector memory field and select:

<Altera Serial Flash Controller instance name>.avl_mem

  • If you are also configuring the FPGA from the EPCS/Q,
  • Set the Nios reset vector offset to a value larger than the size, in bytes, of the FPGA programming file (this is can be determined from the .map file generated with the sof2flash --save option or by generating a .rbf file and determining it's size.)
  • If the FPGA is configuring from serial flash, the configuration data must be at address 0x0.

Be aware that compressed file sizes will differ build to build

  • Regenerate your QSys system and recompile in Quartus


Compiling your Nios II SW:

b/b2/Make_mem_init.jpeg

  • Regenerate your Nios II BSP with the new .sopcinfo file generated above
  • In order to program a bootable executable into the serial flash, the compiler output must packaged into a hex format which can be loaded into the serial flash and the boot loader must be prepended to this file. This can be done directly in the Nios 2 SBT, with make, or manually with utilities provided with the SBT.


Creating the .hex File - Option 1


  • In Eclipse, right click your SW project, select "Make Targets" from the pop-up menu, and click on "Build..."
  • In the "Make Targets" window, select "mem_init_generate", then click build.



  • This will build the project and create a "mem_init" directory in the project directory. The "mem_init" directory will create a loadable .hex file for each memory type in the system. The hex file with the same name as the Altera Serial Flash Controller QSys instance is the file needed to create the .jic file. In the example project, this is the file epcq_controller.hex.


Creating the .hex File - Option 2


  • At the Nios II Shell command line run make with "mem_init_generate" as follows

make mem_init generate

  • This will build the project and create a "mem_init" directory in the project directory. The "mem_init" directory will create a loadable .hex file for each memory type in the system. The hex file with the same name as the Altera Serial Flash Controller QSys instance is the file needed to create the .jic file. In the example project, this is the file epcq_controller.hex.


Creating the .hex File - Option 3


  • Recompile your SW project in the Nios II SBT or at the command line with make.
  • Convert the Nios II .elf to a .flash with the elf2flash command below.

Set the base address and the reset address to the absolute address of the Nios II reset vector. This is the computed "Reset vector:" field in the Nios II configuration GUI. Anything else will result in a .flash file with incorrect addresses.

elf2flash --input=<Nios ELF file name> --output=<.flash file name> \

--base=<EPCQ base address from Qsys memory map> \

--end=<EPCQ end address from Qsys memory map> \

--reset=<Nios II reset vector> \

--boot=<ACDS install path>/ip/altera/nios2_ip/altera_nios2/boot_loader_cfi.srec --save

  • Convert the .flash file to an Intel Hex file

nios2-elf-objcopy --input-target srec --output-target ihex <.flash file name> <.hex file name>


Creating the .jic file:


  • In Quartus, open the Convert "Programming File..." utility
  • Set the "Programming file type:" to "JTAG Indirect Configuration File (.jic)"
  • In "Input files to convert" select "Flash Loader", click "Add Device..." and choose your target FPGA device
  • If you are configuring the FPGA from the serial flash:
  • In "Input files to convert" select "SOF Data", click "Add File..." and select your FPGA .sof file
  • -With "SOF Data" selected, click "Properties", in the "SOF Data Properies dialogue box:
  • -Set "Address mode for selected pages to" to "Start"
  • Set "Start address (32-bit hexidecimal:) to 0x0.
  • In "Input files to convert" click "Add Hex Data", in the "Add Hex Data" dialogue box:
  • Set "Addressing mode" to "Absolute addressing"
  • Select your hex file using the "..." button next to the "Hex file" field
  • Click "OK"
  • Check "Create Memory Map File". This is useful for debugging.
  • Generate the .jic file and program it into the serial flash with the Quartus Programmer


Using the Example Project


  • Plug the BeMicroSDK board into a serial port on your computer.
  • Program the .jic file into the BeMicroSDK board using the Quartus II Programmer.
  • Press the "RECFG" button on the BeMicroSDK board to reconfigure the Cyclone V FPGA from the serial flash.
  • Launch the nios2-terminal and observe the terminal output.
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‎06-24-2019 07:09 PM
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