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CPRI 10G Soft PCS Reference Design Arria V 13.1

CPRI 10G Soft PCS Reference Design Arria V 13.1


The hard PCS in Arria V FPGAs support up to 6.5536 Gbps and the standard PCS available does not support the 10G functionality. To implement 10.1376 Gbps, the transceiver is configured to use a hard PMA and a soft PCS implemented in the FPGA core. This Altera CPRI 10G Soft PCS Arria V reference design demonstrates the configuration and integration between the following components:

  • Arria V Transceiver Native PHY - Hard PMA
  • Arria V 10G Soft PCS
  • Elastic Sync FIFO
  • CPRI frame Generator/Checker (Simulation)

Figure 1.0 Overview of Reference Design with Soft PCS 

Functional Description

Hard PMA

The Arria V Transceiver NativePHY is used in this reference design. In the MegaCore, the PMA mode is selected with data rate at 10137.6 Mbps and its data width at 64bit such that the clocks output would be at 158.4MHz. External Tx PLL option is chosen to allow flexibility (easy modification for PLL sharing for multiple channels). To complete the transceiver setup, an external Tx PLL is instantiated in the top-level as well as the reset controllers and the reconfiguration controller. 

Soft PCS

The soft PCS is implemented in the FPGA core and connected to the 64bit hard PMA. On the other end, it is connected to the Elastic Sync FIFO through 66bit interface with data valid. 

Figure 2.0 Architecture of 10G Soft PCS 

For more information about the PCS 10G architecture please refer to Stratix V device handbook

Elastic Sync FIFO

The Elastic Sync FIFO is an additional logic in this design to ease the usability of the soft PCS solution. Functions of the this block including:

  • Convert 66bit with data valid (158.6 MHz) domain to/from 66bit without data valid (153.6 MHz) domain. 66bit is consisting of 64bit data + 2bit control
  • Phase compensation between clock 158.6 MHz and 153.6MHz, automatically re-synchronize if necessary
  • Delay measurement across FIFO

CPRI Frame Generator/Checker

The CPRI Frame Generator generates continuous 10ms Radioframe pulses with the appropriate comma characters /S/, /T/ for link testing. The CPRI Frame checker checks for correct boundary of consecutive 5 correct comma characters and report the link status. Both of the modules are used only in simulation for this design but they are synthesizable. 

Simulation Support

Modelsim SE simulation script is located under <reference design folder>/src_xcvr/pma_av_sim/mentor msim_setup.tcl 

Timing Constraint (SDC)

SDC timing script is located under <reference design folder>/project/top.sdc. To modify the design, user may need to adjust the constraint accordingly to their preference of top-level clock and module naming. Additional fitter constraint may be needed, please refer to <reference design folder>/project/cpri_avgt_10g_soft_pcs.qsf 

Inquiry / Obtaining the Reference Design.

Please find the Arria V CPRI 10G Soft PCS design in Altera Design Store or contact your local Altera Sales.

Note: This reference design is now compatible with QuartusII 16.0.


Download readme here.


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© [2013] Altera Corporation. QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Version history
Last update:
‎06-24-2019 11:25 PM
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