The hard PCS in Arria V FPGAs support up to 6.5536 Gbps and the standard PCS available does not support the 10G functionality. To implement 10.1376 Gbps, the transceiver is configured to use a hard PMA and a soft PCS implemented in the FPGA core. This Altera CPRI 10G Soft PCS Arria V reference design demonstrates the configuration and integration between the following components:
Arria V Transceiver Native PHY - Hard PMA
Arria V 10G Soft PCS
Elastic Sync FIFO
CPRI frame Generator/Checker (Simulation)
Figure 1.0 Overview of Reference Design with Soft PCS
The Arria V Transceiver NativePHY is used in this reference design. In the MegaCore, the PMA mode is selected with data rate at 10137.6 Mbps and its data width at 64bit such that the clocks output would be at 158.4MHz. External Tx PLL option is chosen to allow flexibility (easy modification for PLL sharing for multiple channels). To complete the transceiver setup, an external Tx PLL is instantiated in the top-level as well as the reset controllers and the reconfiguration controller.
The soft PCS is implemented in the FPGA core and connected to the 64bit hard PMA. On the other end, it is connected to the Elastic Sync FIFO through 66bit interface with data valid.
The Elastic Sync FIFO is an additional logic in this design to ease the usability of the soft PCS solution. Functions of the this block including:
Convert 66bit with data valid (158.6 MHz) domain to/from 66bit without data valid (153.6 MHz) domain. 66bit is consisting of 64bit data + 2bit control
Phase compensation between clock 158.6 MHz and 153.6MHz, automatically re-synchronize if necessary
Delay measurement across FIFO
CPRI Frame Generator/Checker
The CPRI Frame Generator generates continuous 10ms Radioframe pulses with the appropriate comma characters /S/, /T/ for link testing. The CPRI Frame checker checks for correct boundary of consecutive 5 correct comma characters and report the link status. Both of the modules are used only in simulation for this design but they are synthesizable.
Modelsim SE simulation script is located under <reference design folder>/src_xcvr/pma_av_sim/mentor msim_setup.tcl
Timing Constraint (SDC)
SDC timing script is located under <reference design folder>/project/top.sdc. To modify the design, user may need to adjust the constraint accordingly to their preference of top-level clock and module naming. Additional fitter constraint may be needed, please refer to <reference design folder>/project/cpri_avgt_10g_soft_pcs.qsf