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CPRI IP v6 Latency Formula & Calculation Example Draft

CPRI IP v6 Latency Formula & Calculation Example Draft



Contents

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Introduction

This page provides the following information to help user to understand and calculate their total delay budget of system with CPRI IP v6:

  • Fixed latency values of different sub-components within CPRI v6 IP
  • Fixed latency values of other collateral products (IQ Mapper/DeMapper, Compression blocks) of CPRI v6 solutions
  • How-to use the measurement features
  • How-to use the calibration features
  • Examples of calculating the total delay budget of CPRI IP v6 solution

L1 Latency

Figure 1: Components of entire L1 and Latency Term Definition

d/de/L1_SAPs.png


Table 1: Latency Components and its definition

L1 PartDescriptionLatency ComponentSub Components
8b10b variantsFor 614.4, 1228.8, 2457.6, 3072, 4916.2, 6144 and 9830.4 Mbps
Full TxFull Transmitter pathT_TX_8G_L1T_TX_MO_8G_L1 + T_TX_PO_8G_L1
PHY TxPhysical only Transmitter pathT_TX_PO_8G_L1T_TX_8G_PCS + T_TX_PMA
MAC TxMAC Only Transmitter pathT_TX_MO_8G_L1T_TX_FRM + T_TX_8G_M2P
Full RxFull Receiver pathT_RX_8G_L1T_RX_PO_8G_L1 + T_RX_MO_8G_L1
PHY RxPhysical only Receiver pathT_RX_PO_8G_L1T_RX_PMA + T_RX_8G_PCS
MAC RxMAC only Receiver pathT_RX_MO_8G_L1T_RX_8G_M2P + T_RX_DFRM
64/66b variantsFor 8110.08, 10137.6 and 12165.12 Mbps
Full TxFull Transmitter pathT_TX_10G_L1T_TX_MO_10G_L1 + T_TX_PO_10G_L1
PHY TxPhysical only Transmitter pathT_TX_PO_10G_L1T_TX_10G_PCS + T_TX_PMA
MAC TxMAC Only Transmitter pathT_TX_MO_10G_L1T_TX_FRM + T_TX_10G_M2P
Full RxFull L1 Receiver pathT_RX_10G_L1T_RX_PO_10G_L1 + T_RX_MO_10G_L1
PHY RxPhysical only Receiver pathT_RX_PO_10G_L1T_RX_PMA + T_RX_10G_PCS
MAC RxMAC only Receiver pathT_RX_MO_10G_L1T_RX_10G_M2P + T_RX_DFRM

Table 2: Sub-component Latency Value according to device family and line bit rate

Latency ComponentDeviceLine bit rate (Mbps)Core clockPCS clockUIRemarks
T_TX_FRMAllAll4-160
T_TX_8G_M2PAll614.4tx_8g_ex_delay + 0.5-(tx_8g_ex_delay x 40) + 20
All1228.8 - 9830.4tx_8g_ex_delay + 2-(tx_8g_ex_delay x 40) + 80
T_TX_10G_M2PAll8110.08, 10137.6, 12165.12tx_10g_ex_delay + 3-(tx_10g_ex_delay x 40) + 120
T_TX_8G_PCSGen V614.40.75-30
1228.8 - 9830.42-80
Arria 10614.40.75-30
1228.8 - 9830.42-80
T_TX_10G_PCSGen V8110.08, 10137.6, 12165.12-6.8272
Arria 10-6.8272
T_TX_PMAGen V614.41.325-53Assume XCVR_BITSLIP is not used
1228.8 - 9830.42.075-83
8110.08, 10137.6, 12165.12-3.075123
Arria 10614.41.075-43
1228.8 - 9830.41.975-79
8110.08, 10137.6, 12165.12-3.675147
T_CABLEPlease refer to the medium

specification

T_RX_PMAGen V614.40.65-26Assume XCVR_BITSLIP is not used
1228.8 - 9830.40.775-31
8110.08, 10137.6, 12165.12-1.52561
Arria 10614.40.6125-24.5
1228.8 - 9830.41.0125-40.5
8110.08, 10137.6, 12165.12-1.662566.5
T_RX_8G_PCSGen V614.42-80
1228.8 - 9830.45.5 or 6*-220 or 240*
Arria 10614.41.5-60
1228.8 - 9830.49-360
T_RX_10G_PCSGen V8110.08, 10137.6, 12165.12-7.125285
Arria 108110.08, 10137.6, 12165.12-7.125285
T_RX_8G_M2PAll1228.8 - 9830.4rx_8g_ex_delay + 5-(rx_ex_delay x 40) + 200
T_RX_10G_M2PAll8110.08, 10137.6, 12165.12rx_10g_ex_delay + 4 or 5*-(rx_10g_ex_delay x 40) + 160 or 200*
T_RX_DFRMAllAll5-200
  • Gen V device family including Stratix V, Arria V and Cyclone V devices
  • tx_8g_ex_delay or tx_10g_ex_delay is the Soft Tx FIFO latency value in register 0x50 TX_EX_DELAY - tx_ex_delay value
  • rx_8g_ex_delay or rx_10g_ex_delay is the Soft Rx FIFO latency value in register 0x54 RX_EX_DELAY - rx_ex_delay value
  • (*) Additional 0.5 clock cycle (or equivalent value in UI) if the register 0x4C RX_DELAY bit[16] rx_byte_delay is read as 1'b1

Other Components Latency

7/7b/IQMAP_SAPs.png


Table 3: IQ Mapper/DeMapper Component latency

Latency ComponentDescriptionCalculation
T_TX_MAPLatency across the generated IQ Mapper RTL(Number of bits in current line bit rate basic frame/32) + 4 cpri_clkout clock cycle. For example,

614.4Mbps, number of bits per basic frame is 128. So latency is (128/32)/4 = 8 cpri_clkout clock cycle

T_AUX_DAdditional latency incur when IF_LATENCY value is not zeroLatency value is IF_LATENCY value
T_RX_MAPLatency across the generated IQ DeMapper RTLValue is identical to T_TX_MAP
T_TX_CUSLatency across the Tx adaptation logicNo calculation available. Latency value is user design dependant
T_RX_CUSLatency across the Rx adaptation logicNo calculation available. Latency value is user design dependant

Table 4: IQ Compression block latency

ComponentDescriptionLatency Value
ccamIQ Compression block1 clock cycle
ceamIQ DeCompression block1 clock cycle

Delay measurement for Soft FIFOs

Please refer to User Guide Chapter 3 Extended Delay Measurement, Deterministic Latency and Delay measurement sections

Delay calibration

Please refer to User Guide Chapter 3 Tx Bitslip Delay

Examples of Total Delay Budget Calculation

Table 5: Stratix V 9.8304Gbps Total Delay Budget Calculation Example

a/a8/Ex_sv.png


Table 6: Arria 10 10.1376Gbps Total Delay Budget Calculation Example

c/cb/Ex_a10.png


Disclaimer

The information provided in this page will only compliant to the latest version of CPRI IP v6 (15.1.313) in release page. In addition, these numbers will work in

hardware and there may be discrepancies with simulation model. Should you need further information, please contact engineering.

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 06:25 PM
Updated by:
 
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