This page provides the following information to help user to understand and calculate their total delay budget of system with CPRI IP v6:
Figure 1: Components of entire L1 and Latency Term Definition
Table 1: Latency Components and its definition
Table 2: Sub-component Latency Value according to device family and line bit rate
Table 3: IQ Mapper/DeMapper Component latency
614.4Mbps, number of bits per basic frame is 128. So latency is (128/32)/4 = 8 cpri_clkout clock cycle
Table 4: IQ Compression block latency
Please refer to User Guide Chapter 3 Extended Delay Measurement, Deterministic Latency and Delay measurement sections
Please refer to User Guide Chapter 3 Tx Bitslip Delay
Table 5: Stratix V 9.8304Gbps Total Delay Budget Calculation Example
Table 6: Arria 10 10.1376Gbps Total Delay Budget Calculation Example
The information provided in this page will only compliant to the latest version of CPRI IP v6 (15.1.313) in release page. In addition, these numbers will work in
hardware and there may be discrepancies with simulation model. Should you need further information, please contact engineering.
For more complete information about compiler optimizations, see our Optimization Notice.