Showing results for 
Search instead for 
Did you mean: 
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

CPRI RE Reference Design Arria V 13.0

CPRI RE Reference Design Arria V 13.0


This Altera CPRI Radio Equipment (RE) reference design demonstrates the operation of the Altera CPRI MegaCore function instantiated as an RE. The design highlights dynamic rate configuration of the Altera transceivers and how this feature can be used to implement a RE Slave capable of acquiring Frame Synchronization to any rate, automatically.

The reference design has the following features:

  • Configures the RE slave on the Arria V GX device on an Arria V GX development board.
  • Provides software control using the Nios II embedded processor.
  • Automatic acquisition of Frame Synchronization for the following data rates:

1228.8 Mbps

2457.6 Mbps

3072.0 Mbps

4915.2 Mbps

6144.0 Mbps

This application note demostrates how to install and run the CPRI RE reference design. It describes the system used for this design and shows you how to use the hardware and software. This application note contains the following sections:

  • General Description
  • Functional Description
  • Clocking
  • Using the Reference Design
  • Document Revision History

Obtaining the Reference Design.

Please contact your local Altera Sales.

General Description

The RE slave is configured on an Arria V GX device. The design uses a QSYS subsystem that includes a Nios II processor. The embedded processor is used to program the CPRI IP core and monitor its status.

The RE slave targets an Arria V GX device on the Arria V GX Starter Kit. This starter kit has an HSMC connector which carries serial channels. An SFP-HSMC daughter card is connected to the HSMC port. This card has an SFP cage with the cpacity for up to four SFP+ modules. This design uses only one SFP slot. The CPRI protocol is carried over a fiber cable driven by an SFP+ module. To demostrate its functionality, this RE slave design needs an REC Master to connect to. When connected to an REC Master, the RE slave will acquire frame synchronization t the master's data rate.

The frame synchronization is confirmed by reading the register CPRI_STATUS at offset 0x4 of the CPRI RE MegaCore. The register reports the status of the frame synchronization state machine.

Figure 1.0 is a diagram of the hardware setup. In addition to the Arria V GX board and the SFP-HSMC daughter card, the diagram shows the clock conditioner board. The clock conditioner board filters noise and jitter on a 15.36 MHz signal and generates a clean 122.88 MHz signal. The cleaned 122.88 MHz is used as the reference clock for the transmit transceiver PLL. The transceiver used in the Arria V GX will recomver a clock from the serial bit stream. This clock is converted into a received parallel clock. The frequency of the receiver paralle clock depends on the CPRI data rate. This design includes a module that divides down the recovered parallel clock to a 15.36 MHz clock. The clock connections to and from the clock conditioner board are carried over SMA cables. The clocking is described in detail in the Clocking section.

Figure 1.0 Hardware Setup

Functional Description

Figure 2.0 shows a high level block diagram of the CPRI RE reference design. This section will describe each of the main and sub-blocks in the design.

Figure 2.0 High Level Block Diagram


The CPRI_RE has the following features:

  • Operation mode: Slave(RE Slave)
  • Line rate (Gbit/s): 6.144
  • Transceiver reference clock frequency: 122.88 MHz
  • Enable automatic round-trip delay calibration logic: No
  • Include automatic round-trip delay calibration logic: No
  • Include HDLC block: No
  • Include MAC block: Yes
  • Mapping mode(s): Basic
  • Number of antenna/carrier interfaces: 0
  • Include Vendor Specific Space (VSS) access through CPU interfaces: No

The focus of this reference design is to demonstrate how using dynamic reconfiguratioin of the altera Transceivers is used to implment a CPRI RE Slave capable of automaticaly acquiring frame synchronization. For this reason, no antenna/carrier interfaces were selected. The auxiliary interface is available for both reception and transmission of Control Words and IQ samples. This design ties low the transmit auxiliary interface. Other reference designs are available which demostrate the use of the antenna channel, the auxiliary, the MII, and the CPU interfaces.


The control unit is implemented as a QSYS subsystem. It facilitates access to the CPRI RE slave register space. This reference design includes a small C program which is executed on the Nios II processor. The program and supported commands are explained in more detail in the section, “Running the Reference Design”. The control unit is clocked with a 75 MHz clock. The control unit consists of the following components.

Nios II Processor – The C program, available with this reference design is executed on the embedded processor. The program provides basic read and write access to the CPRI RE slave register space. The features used in the Nios II processor can be viewed by bringing up the control_unit design in QSYS.

JTAG UART - This component provides the mechanism for the FPGA to communicate with the nios2-terminal. The nios2-terminal is the user interface to the CPRI RE software program.

MEM – 64Kbyte of internal memory. This is used to store the compiled C program which is executed by the Nios II processor.

Avalon Bridge – provides connectivity to the CPRI RE slave CPU interface

Stats Register – Registers the following CPRI RE status signals. See the section, “Register Map” for the address to each status register.



















MISC CTL – This block provides software control to the CPRI RE resets and also provides software control to the SFP+ module on the HSMC-SFP daughter card. See the section, “Register Map” for the address to the registers that drive these control signals.













Version history
Last update:
‎06-27-2019 06:32 PM
Updated by: