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CPRI v6 Build 15.0 to 15.1 Migration Guide

CPRI v6 Build 15.0 to 15.1 Migration Guide


Contents

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How-to Migrate 

1) Backup 15.0 project, especially the CPRI IP top-level file and SDC constraint.

2) If you are migrating to 15.1 for CycloneV, ArriaV, ArriaV GZ and StratixV device family, please complete steps 2a) to 2b) below. Otherwise, skip this step 2) and jump to 3).

a) In 15.0 project, search for generated top level CPRI IP file you named. It will be in <project folder>/<top level name>.v or .vhd.

b) Edit this file, and change the first line %CPRI v6.0 v15.0% to %CPRI v6.0 v15.1%

3) Open 15.0 project in QII 15.1 with CPRI IP 15.1.258 patched.

4) Re-generate CPRI 15.0 IP to 15.1 using one of these methods:

a) Method I (For all device family)

i) Under Project Navigator -> IP Components -> Right click "CPRI v6.0" IP and choose "Edit in Parameter Editor"

ii) All 15.0 original parameter settings will load in 15.1, click generate to re-generate the IP

b) Method II (Arria10 device family only)

i) Launch IP Upgrade Tool in Project Navigator or look for Project Tab -> Upgrade IP Components

ii) Select the CPRI v6.0 with version 15.0 and perform automatic upgrade. Alternatively, "upgrade in Editor" will bring you back to Method I above.

5) Once regeneration is completed, you should proceed to check on the new CPRI v15.1 top-level file and the SDC constraint file. Notice the difference between the two version and you should make appropriate modification to your design following the sections below.

Interface Changes 

Port15.1 ChangesRemark
cpri_10g_coreclkPort name changed to cpri_coreclkThis port is available in 8.1108 and 101376 Gbps
tx_analogreset_ackNew port in this releaseThis port is used in line bit rate auto-negotiation and only available in condition (A)
rx_analogreset_ackNew port in this releaseThis port is used in line bit rate auto-negotiation and only available in condition (A)
xcvr_recovered_clkPort removed based on configurationThis port is available in Slave mode only
reconfig_clkPort removed based on configurationThis port is available in condition (B)
reconfig_resetPort removed based on configurationThis port is available in condition (B)
xcvr_reset_txPort removed permanentlyDangling port, refer to reset scheme in Figure 3.3 of CPRI UserGuide 2015.09.29
xcvr_reset_rxPort removed permanentlyDangling port, refer to reset scheme in Figure 3.3 of CPRI UserGuide 2015.09.29
cpu_addressBehavior may change based on configurationAddress type depends on Avalon-MM addressing type. See Register Changes section
Condition (A)

Arria10 device family

General -> Line bit rate auto-negotiation is turned on

(see Arria10 transceiver PHY User Guide Figure 4-1 for more information)

Condition (B)

CycloneV, ArriaV, ArriaV GZ and StratixV device family

General -> Turn on Line bit rate auto-negotiation, OR/AND

Interfaces -> Enable Start-up sequence State Machine

Arria10 device family

General -> Turn on Line bit rate auto-negotiation, OR/AND

Interfaces -> Enable Start-up sequence State Machine, OR/AND

Interfaces -> Enable ADME, transceiver capability, control and status register access

Register Changes 

  1. No changes to existing register listing and property, addresses at 0x60, 0x64, 0x6C and 0x70 are now reserved for future expansion.
  2. Note: Management (CSR) interface now allows "Word" or "Byte" addressing type, default type for 15.0 and 15.1 is Word addressing. Choose Word addressing if migrating from 15.0, no modification needed to design or software. If type is changed to Byte addressing, hardware and software in original design will required appropriate modification.


Version history
Revision #:
1 of 1
Last update:
‎06-24-2019 11:37 PM
Updated by:
 
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