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CPRI v6 Build 15.1.258
CPRI v6 Build 15.1.258
Migration Guide
If you are migrating from a previous release to the latest version, please refer to the link below:
Changelog
A) New features:
1) New v6.1 8110.08 Gbps (Option 7A) line bit rate support for Stratix V and Arria 10 device families. See Figure 1.
B) Enhancements:
1) New transceiver analog reset acknowledge port "tx_analogreset_ack" and "rx_analogreset_ack" for line bit rate auto-negoatiation feature
2) Port name change for "cpri_10g_coreclk" to "cpri_coreclk" in 10.1376 or 8.11008 Gbps configuration
3) CPU Interface Avalon-MMM new addressing type option, option are "word" or "byte". See Figure 2
4) Removal of reconfig_clk, reconfig_reset ports and transceiver management interface when line bit rate auto-negotiation and startup sequence state machine are not enabled
5) Enable ADME, transceiver capability, control and status register access. This option expose the transceiver management interface, reconfig_clk/reconfig_reset ports and supercede 4). See Figure 3.
C) Bug fixes:
1) Line Bit Rate Auto-Negotiation during configuration from 10.1376 Gbps to other rates with following scenarios:
a) Assertion of rx_freq_alarm when the link reached Hyperframe synchronization
b) Link lost synchronization
2) Ethernet PCS with GMII with following scenario:
a) Not able to transmit Jumbo packet in 614.4, 9830.4 and 10137.6 Mbps
3) CPU Interface and registers with following scenario:
a) Write/read transaction to address other than 0x30, 0x34 and 0x38 does not assert waitrequest. Now change to compliant to Avalon-MM specification chapter 3.5.1
b) Register INTR (0x00) bit 16,17 and 18 incorrect _pending value
c) Register L1_STATUS (0x04) bit 8,9,10,11 and 12 incorrect _hold value
4) Rx state machine toggle between 0 and 1 when new scramble seed is transmitted with protocol version active at 2. De-scramble unable to retrieve new seed on Rx.
5) Simulator VCS or NCSIM may halt compilation due to error related to "always_ff" syntax
Graphic User Interface (GUI) Changes
Figure 1 New Line Bit Rate Option 7A
Figure 2 New CPU Avalon-MM Addressing Type
Figure 3 Enable access to transceiver internal control for Arria10 only
For more complete information about compiler optimizations, see our Optimization Notice.