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CPRI v6 Build 17.0.260

CPRI v6 Build 17.0.260

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A) New features:

1) Support of Stratix 10 devices

a) L-tile up to line bit rate Option 8 - 10.1376Gbps (QII 17.0IR3 only)


- Static line bit rate support only, rate auto-negotiation not available

- Line bit rate Option 1 - 614.4 Mbps not available

- Simplex Tx/Rx mode not available

B) Bug fixes:

1) Fix LCV counter which causes deadlock in frame re-synchronization (see Errata 475322)

2) Fix register XCVR_BITSLIP (0x5C) - tx_bitslip_en is not connected to transmitter (see Errata 475618)

3) Fix low Ethernet thoughput (MII only) in lower line bit rates (<3.072Gbps) (see Errata 464675)

4) Fix reading register CTRL_INDEX/TX_CTRL/RX_CTRL (0x30,0x34,0x38) hang issue (see Errata 447177)

5) Fix double assertion on aux_tx_rfp_sync that causes link fail (see Errata 443827)

6) Fix HDLC serial interface at 240kbit/s (001) issue (see Errata 479150)

7) Fix register BIT_RATE_CONFIG (0xC) not in Read-only mode (see Errata 478490)

8) Fix aux_tx_err false assertion when in IF_LATENCY > 0 mode (see Errata 480483)

9) Fix link issue in line bit rate Option 7A/8 when rate auto-negotiation is turned on (simulation only)(see Errata 477813)

C) Enhancement:

1) Improve Tx/Rx FIFO re-synchronization logic for better consistency in FIFO initial delay (see Errata 472785)

2) Additional LOS/LOF status bit added to register FLSAR (0x2C)

D) Feature changes:

1) Removal of 614.4 Mbps support in Arria 10

2) Removal of Tx local clock division factor value (2,4,8) for lower line bit rate (<5Gbps) Arria 10 (see Errata 475609)

3) Removal of Rx recovered clock source option for Arria 10 (see Errata 475622)

E) Documentation:

1) New User Guide based on 17.0 will be available soon


For existing bug/limitation in this build, please see this link.

Version history
Last update:
‎06-24-2019 11:44 PM
Updated by: