The following table records the known issues for CPRI v6 IP, full description of each issue is described later in this page. If you need a patch(fix) of this issue in your current build, please contact engineering for support.
|Errata no||Issued Date||Version/Build||Description||Fix in|
|376019||11 May, 2016||15.1.313||Ethernet Tx PCS with MII interface may experience packet drop||16.0.249|
|376021||11 May, 2016||15.1.313||Ethernet Rx PCS with MII interface may experience state machine deadlock||16.0.249|
|376061||12 May, 2016||15.1.313||Ethernet Tx PCS with GMII interface may experience packet drop||16.1.275|
|376285||12 May, 2016||15.1.313||Ethernet Tx and Rx PCS with GMII interface could not reset thoroughly||16.1.275|
|377102||17 May, 2016||15.1.313||Ethernet Tx with MII interface at 3072Mbps may corrupt some packet(s)||16.0.249|
|380077||30 May, 2016||15.1.313||Stratix V line bit rate auto-negotiation to 9.8304Gbps (or lower rate) may not work||16.0.249|
|410745||1 Mar, 2017||16.0.249||Incorrect LOS LOF RAI value during reset||16.1.275|
|436960||1 Mar, 2017||16.0.249||LCV counter has incorrect bit width||16.1.275|
|440946||1 Mar, 2017||16.1.275||Vendor Specific Slot may be overridden when Pointer-P = 0||16.1.285|
|440949||1 Mar, 2017||16.1.275||vs_tx_rdy has no assertion or absent on certain basic frame||16.1.285|
|447072||22 Mar, 2017||16.1.285||SDC error for single-trip delay calibration||17.0.260|
|475322||7 Aug, 2017||16.1.285||LCV counter causes deadlock in frame re-synchronization||17.0.260|
|475618||7 Aug, 2017||16.1.285||Register (0x5C) XCVR_BITSLIP - tx_bitslip_en is not connected to transmitter||17.0.260|
|464675||7 Aug, 2017||16.1.285||Ethernet MII (<3Gbps) has low throughput||17.0.260|
|447177||7 Aug, 2017||16.1.285||Register (0x30/34/38) CTRL_INDEX/TX_CTRL/RX_CTRL hang during read operation||17.0.260|
|443827||7 Aug, 2017||16.1.285||Double assertion on aux_tx_rfp_sync may cause link fail||17.0.260|
|479150||7 Aug, 2017||16.1.285||HDLC serial interface bandwidth issue at 240kbit/s (001)||17.0.260|
|478490||7 Aug, 2017||16.1.285||Register (0xC) BIT_RATE_CONFIG not in Read-only mode||17.0.260|
|480483||7 Aug, 2017||16.1.285||aux_tx_err port give false assertion when IF_LATENCY > 0 mode is used||17.0.260|
|477813||7 Aug, 2017||16.1.285||(Simulation) Link issue in line bit rate option 7A/8 when rate auto-negotiation is turned on||17.0.260|
|472785||7 Aug, 2017||16.1.285||(Enhancement) Improve soft FIFO initial delay consistency after re-synchronization||17.0.260|
|435635||7 Aug, 2017||16.1.285||(Enhancement) Additional LOS/LOF bits added in register (0x2C) LFSAR||17.0.260|
|475609||7 Aug, 2017||16.1.285||Disable Tx local clock division factor (2,4,8) for <5Gbps in Arria 10||17.0.260|
|475622||7 Aug, 2017||16.1.285||Disable Rx recovered clock option for Arria 10||17.0.260|
|484198||16 Aug, 2017||17.0.260||"VCCR_GXB and VCCT_GXB supply voltage for the Transceiver" Option is redundant in CPRI GUI||TBD|
|487898||25 Aug, 2017||17.0.260||Line bit rate auto-negotiation should be disabled for 1.2288Gbps in Arria 10/Stratix 10||TBD|
|507451||1 Nov, 2017||17.0.260||Testbench generation failure in Windows Platform||TBD|
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.