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CVO IP video mode detection and switching feature

CVO IP video mode detection and switching feature

Last Major Update

New Release for Stratix V - December 12th 2016 - Quartus II v16.1 Installed 

Design Overview

This design demonstrates: 

a) Video mode detection and switching feature of CVO IP 

b) Run time configure the TPG and Interlace IP to generate difference type of video format 

Here is the top level diagram of the design: 


The Video Source Block contains Test Pattern Generator (TPG), Interlacer IP, and CVO IP. This video source block is used to generate difference type of video formats, which include PAL (SD-SDI), 720p60 (HD-SDI) and 1080p60 (3G-SDI). 

The CVO IP is configuring to three difference video models by using the “video_format.tcl”. The CVO IP will detect the incoming video format and switch the video model accordingly. 

Model 1: 720p60 

Model 2: 1080p60 

Model 3: PAL 

The CVO’s vid_clk is connected to SDI’s “tx_clkout” when transmit 3G-SDI, for other video formats, the CVO’s vid_clk is connected to “tx_dataout_valid”. 

Please take note that the “vid_clk” is not glitch-free in this design, and above connection of "vid_clk" is not recommended for the production.

The “vid_std” signal is an output signal of the CVO, it output the value (e.g SD-SDI = 0, HD-SDI = 1 and 3G-SDI =3) that you configure at Model Standard Register of CVO (address 12), and this signal can be connected to SDI IP (tx_std signal). 

Hardware Setup:


This design was compiled for Quartus Prime v15.1 for Stratix V DSP Development Kit. 

a) SDI_TX (J17) can connect to SDI signal Analyzer 

b) Or the SDI_TX(J17) can connect to SDI_RX(J16) to perform serial loopback test 

Running the Design:

1) Download the design:

v15.1 -> File:SV CVO SDI 15 1

v16.1 -> File:Sample top v16.1.qar

2) Open stp1_sk.stp and download the sof file to FPGA 

3) Open config.tcl file, and modify the “SDI_Mode” parameter for difference video format (1=SD (PAL), 2= HD (720p60), 3=3G (1080p60)).

4) Open system console and change the directory to “.../sample_top_SV_DSP_triple_Rate_15_1/sc_tcl” 

5) Type source config.tcl in TCL Console

6) Connect the SDI_TX (J17) to SDI signal Analyzer and investigate the signals 

7) For serial loopback test, you can verify the following signals from signal tap:

a. “rx_format” (PAL -> 0x1, 720p60 -> 0x7, 1080p60 -> 0xc)

b. “rx_frame_locked” is asserted

Version history
Last update:
‎06-24-2019 11:49 PM
Updated by: