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Configuration Walk-Through - Quartus FPGA Design & Settings

Quartus FPGA Design & Settings

1. This is a simple LED design File:FPP.qar. Copy and paste this .qar into your project directory. Restore this design by going to Project → Restore Archived Project. 

2. Pin assignments are performed in Assignment → Pin Planner. Refer to development kit reference manual for information on pin location if you wish to change pin assignments. 

3. Go to Assignment → Device → Device & pin options → Configuration. Ensure that the correct checkboxes are ticked:

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Note: - Ensure that the configuration scheme matches with the one set in the PFL IP core. 

 

4. Compile the design by going to Processing → Start Compilation to obtain the .sof 

5. You can also open another project revision: led_2 that has a different LED pattern. Compile the design to obtain the other .sof.

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Programming file generation

As we are going to program the design into the CFI flash, we need to generate a programming file that is compatible to the CFI flash: programmer object file (.pof) 

1. Open the Convert Programming File GUI by going to File → Convert Programming Files. 

2. Set as according to the following screenshot:

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Note: 

- The start address for SOF data is 0x80000(in hex) as we just want to store this design in the user hardware 1 as shown in the CFI Memory Map table above. The start address can be modified by going to “Properties”. 

- Options start address is left blank as only the SOF data is programmed into the CFI flash. If you are working with a blank CFI flash, then you have to choose a location to store the option bit so that the PFL IP knows the addresses of your configuration data. Ensure that the options bits are stored in unused portion of the flash device and the start address resides on a 8-KB boundary. The option bit address can be changed by clicking at “Options/Boot info”. 

 

3. Generate the .pof file by clicking on the generate button.

Setting up the development kit

1. Set up the Cyclone V GX development kit according to the factory default settings. You can refer to “Setting up the board” in Chapter 4 of the development kit user guide. 

2. The MSEL pins setting are controlled by MAX V design, however as the default pins setting point to FPP x 16 configuration scheme, no additional action is required.

Demo-Bringing up the design in hardware

The MAX V will now be programmed with the PFL IP core design created above. We will then use the PFL to program the CFI flash and then control the FPGA configuration with the data from CFI flash. 

 

Programming PFL design into MAX V 

1. Ensure the USB Blaster is connected correctly to the JTAG port of the Cyclone V GX development kit. 

2. In Quartus, go to Tools → Programmer. 

3. Configure the hardware setup to point to USB Blaster I/II. 

4. Perform “auto-detect” to detect the physical devices in the JTAG chain. 

5. Right click on the detected MAX V device and choose “change file” 

6. Browse to the generated .pof and click ok. 

7. Tick on “Program/Configure” . 

8. Click start to begin the programming process. 

9. After completion of the programming process, perform “auto-detect” once again. You should be able to see the CFI flash attached to the MAX V device. 

Note: 

- You will be able to restore the original MAX V design by going to <installation directory>\kits\cycloneVGX_5cgxfc7df31es_fpga\examples\max5 and program the max5.pof. 

 

Programming the LED design into CFI flash 

As the CFI flash contains important information, it is advisable to examine out the content of the CFI flash before any flash programming is done so that you will be able to reprogram it back to its original state if any mistake occur. To examine the CFI flash: 

1. Tick on “examine” for the CFI flash detected at step 9 (ensure that no other boxes are ticked). 

2. Click start and wait for the programmer to examine the CFI content. 

3. Right click the examined .pof and choose save. You will be prompted to key in the option bit location (18000). Store this .pof elsewhere for emergency usage. 

4. Right click again and choose “change file”. 

5. Browse to the LED design .pof and click ok. 

6. Tick on “Program/Configure”. 

Note: 

- Make sure you tick only on “Page_0”. Ticking on the upper box will erase the whole CFI flash and reprogram it with only page_0 and option bit. If the option_bits box is ticked, it will create a mismatch between the option bit address in the PFL IP and the CFI flash thus causing the FPP configuration to fail.

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7. Click start to begin the programming process. 

8. Push the dipswitch at SW3.3 to OFF and hit on PGM_Load push button. You will then see the LED design on the board. 

Note: 

- Pushing the dipswitch to OFF indicate 001 at the PGM input of the PFL IP core. This allows the PFL IP to read the configuration data at User Hardware 1 and configuration is triggered by the PGM_Load push button. You can include your own design at the Factory hardware by changing the address in the section IV above. You can then trigger reconfiguration by pushing the dipswitch to ON (000) and hit the PGM_Load push button. You can then restore the CFI flash content with the .pof examined out earlier.

JTAG Configuration Mode

Theory

JTAG configuration is the simplest configuration scheme which is available in all Altera FPGA families. Altera FPGA is designed in such a way to allow JTAG instructions precedence over other configuration schemes. This means that JTAG configuration can take place without waiting for other configuration schemes to complete. However, as the device CRAM is directly configured with JTAG configuration scheme, the device will lose its configuration data after a power cycle. Hence, JTAG configuration scheme is usually used for testing and development purpose only. The figure below shows the connection required for a successful JTAG configuration:

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Note: Image taken from Cyclone V handbook. Other devices might require the resistors to be pulled up to different VCC. Please refer to the respective handbook/Pin connection guideline.

 

As shown in the figure, a download cable is used (usually USB Blaster I/II) to transfer configuration data from an external host (PC) to the FPGA via the JTAG pins (TDI, TDO, TCK, TMS)

Hands-On with JTAG Configuration

As JTAG configuration scheme does not require any specific setting and has precedence over other configuration scheme, you can use any of the designs included in the configuration schemes above.

Required hardware & software

Hardware: Any development kit 

Software: Quartus Prime 16.0

Quartus FPGA Design & Settings

1. Copy and paste any .qar from the three configuration schemes above into your project directory. Restore the design by going to Project → Restore Archived Project. 

2. Pin assignments are performed in Assignment → Pin Planner. Refer to development kit reference manual for information on pin location if you wish to change pin assignments. 

3. Compile the design by going to Processing → Start Compilation to obtain the .sof

Setting up the development kit

1. Set up the development kit according to the factory default settings. You can refer to “Setting up the board” in Chapter 4 of the development kit user guide. 

2. The MSEL pins setting are irrelevant for JTAG programming. However, do ensure that the MSEL pins setting are valid (you can any of the listed pins setting in the MSEL pin table in the configuration chapter of the device handbook). 

Note: - You can ignore this if you are using the MAX 10 design.

Demo-Bringing up the design in hardware

1. Ensure that USB Blaster is connected correctly to the JTAG port of the Development Kit. 

2. In Quartus, go to Tools → Programmer. 

3. Configure the hardware setup to point to USB Blaster I/II. 

4. Perform “auto-detect” to detect the physical device in the JTAG chain. 

5. Right click on the detected FPGA device and choose “change file”. 

6. Browse to the generated .sof and click ok. 

7. Tick on “Program/Configure” and click start. 

8. You should see the design running once the programming process is complete.

 

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Last update:
‎11-01-2020 12:54 PM
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