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Configuration Walk-Through

Configuration Walk-Through



Configuration in Altera’s context refers to the process which the device has to go through after power up before entering into user mode. As FPGA consist of SRAM volatile memory, it is unable to retain data after a power cycle. This means that the device has to be configured upon each power cycle/power up and due to this requirement, the configuration data must be stored in certain non-volatile flash device such as Altera EPCS/EPCQ, CFI flash and etc so that the FPGA can be configured after a power cycle/power up.Introduction

Objectives

This walkthrough document is created as a supplement to the current device handbook, giving new users a general idea of the several configuration scheme offered by Altera. This document highlights the settings and notes to be taken into consideration for each configuration scheme and serve as a template for users to expand in order to suit their applications.

Prerequisites

Quartus Prime software download: https://www.altera.com/products/design-software/fpga-design/quartus-prime/download.html 

USB Blaster I/II installation guide: https://www.altera.com/support/support-resources/download/drivers/usb-blaster/dri-usb-blaster-vista....

Internal Configuration Mode (only available in MAX 10)

Theory

Internal configuration is one of the two configuration schemes offered by MAX 10 devices, the other being the usual JTAG configuration.

Unlike the other FPGA, MAX 10 is a hybrid between CPLD-FPGA and thus has an internal flash that resides in the device itself

This feature allows configuration data to be stored into the configuration flash memory (CFM). CFM is a non-volatile flash that can store up to two compressed configuration images depending on the compression and device size. During internal configuration, MAX 10 device will load the CRAM with configuration data from CFM.

Unlike the previous devices in the MAX family, MAX 10 has configuration pins (nCONFIG, nSTATUS and CONF_DONE) that are required to be pulled up in order for the internal configuration to be successful.

Initialization Configuration Bits (ICB)

ICB is used to store the configuration related information due to the removal of MSEL pins and absent of fuse. The ICB will be part of the .pof that will be programmed into the internal flash during POF programming. List of ICBs include: 

• Set I/O to weak pull-up prior usermode 

• Configure device from CFM0 only. 

• User secondary image ISP data as default setting when available 

• Verify protect 

• Allow encrypted POF only 

• JTAG Secure 

• Enable Watchdog 

• Watchdog value


Note: This ICB setting can be accessed in Quartus from Assignment → Device → Device & Pin Options → Configuration → Device Options

Hands-On with Internal Configuration

Required hardware & software

Hardware: MAX 10 Development Kit 

Software: Quartus 16.0

Quartus FPGA Design & Settings

1. This is a simple blinking LED design:File:Internal Configuration.qar . Copy and paste this .qar into your project directory. Restore this design by going to Project  Restore Archived Project. 

2. Pin assignments are performed in Assignment → Pin Planner. Refer to development kit user guide for information on pin location if you wish to change pin assignments. 

3. Go to Assignment → Device → Device & pin options → General. Ensure that the correct check-boxes are ticked.

Note: 

- Enable nCONFIG, nSTATUS and CONF_DONE pins must be ticked so that they can function as configuration pins in user mode (nCONFIG is usually use to reset the device). Otherwise, they are available as user I/O pin during user mode. 

- Do not tick on “Enable JTAG pin sharing” as you might lose access to JTAG pins in user mode due to improper settings.


4. Compile the design by going to Processing → Start Compilation to obtain the .sof and .pof.


Demo- Bringing up the design in hardware

The internal flash of the MAX 10 must be programmed with the .pof file for internal configuration to occur. Once the internal flash is programmed, then internal configuration can be performed by either power cycle or pulsing the nCONFIG pin.


1. Ensure that USB Blaster is connected correctly to the JTAG port of the MAX 10 Development Kit. 

2. In Quartus, go to Tools → Programmer. 

3. Configure the hardware setup to point to USB Blaster I/II. 

4. Perform “auto-detect” to detect the physical device in the JTAG chain. 

5. Right click on the detected device and choose “change file”. 

6. Browse to the generated .pof and click ok. 

7. Tick on “Program/Configure” and click start. 

8. You should see the design running on the development kit after a power cycle.

Active Serial (AS) Configuration Mode

Theory

This is a configuration scheme in which the FPGA devices are configured with data stored in non-volatile serial configuration device known as EPCS/EPCQ/EPCQ-L. EPCS is usually for older devices while EPCQ that has larger density is usually used for newer devices. EPCQ-L is exclusively for Arria 10 FPGAs due to its low power requirement. These serial configuration devices feature a simple four-pin interface and a sample connection is shown in the diagram below. This scheme is considered the simplest configuration mode available after JTAG. It is called an active configuration scheme because FPGA is the master and controls the configuration process. 


Note: Image taken from Cyclone V handbook. Other devices might require the resistors to be pulled up to different VCC. Please refer to the respective handbook/Pin connection guideline. 


There are two methods to store the configuration data into the serial configuration device. The first is actually by performing in-system programming of serial configuration devices through the AS programming interface using a .pof file format. However, this method is not preferred as it requires an additional AS header besides the usual JTAG header.

The second method actually uses only the JTAG header to program the serial configuration device. This is achieved by the Altera Serial Flash Loader (SFL) IP core which acts as a bridge to connect between the JTAG and AS interface in the FPGA. This method requires .jic file format and the programmer will include a SFL image to be configured in the FPGA whenever it detects a .jic file. 

Note: For more explanation on SFL IP core, please refer to AN370: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an370.pdf

Hands-On with Active Serial Configuration

Required hardware & software

Hardware: Cyclone V E development kit (Minor resistor rework is required. Refer to page 8 of the development kit schematic) 

Software: Quartus Prime 16.0

Quartus FPGA Design & Settings

1. This is a simple blinking LED design:File:Active Serial.qar. Copy and paste this .qar into your project directory. Restore this design by going to Project → Restore Archived Project. 

2. Pin assignments are performed in Assignment → Pin Planner. Refer to development kit reference manual for information on pin location if you wish to change pin assignments. 

3. Go to Assignment → Device → Device & pin options → Configuration. Ensure that the correct options are chosen. 

Note: - Incorrect configuration scheme will cause programming failure. - Active Serial x 4 is chosen because the development kit hardware is fitted with EPCQ256. You may also choose Active Serial x 1 scheme as EPCQ devices support both variants. 


4. Compile the design by going to Processing → Start Compilation to obtain the .sof

Programming file generation

The Cyclone V E development kit is built with only the JTAG port connection. Hence in order to program the EPCQ device via the JTAG header, we need to generate the required programming file: JTAG Indirect Configuration File (.jic) 

1. Open the Convert Programming File GUI by going to File → Convert Programming Files 

2. Set as according to the following screenshot:


Notes: - Make sure the mode chosen corresponds to the Quartus setting you set previously - Select the correct configuration device (it should be the same with the one soldered on the development kit) to avoid programming failure. 


3. Generate the .jic file by clicking on the generate button.

Setting up the development kit

1. Set up the Cyclone V E development kit according to the factory default settings. You can refer to “Setting up the board” in Chapter 4 of the development kit user guide. 

2. Change the MSEL pin to Active Serial configuration scheme. You may refer to the configuration chapter of the device (Cyclone V) handbook for the MSEL setting.

Demo-Bringing up the design in hardware

The EPCQ device on the development kit has to be programmed with .jic file. Once it is programmed with .jic file, active serial configuration will automatically occur on the next power cycle /pulsing of the nCONFIG pin.


1. Ensure the USB Blaster is connected correctly to the JTAG port of the Cyclone V E development kit. 

2. In Quartus, go to Tools → Programmer. 

3. Configure the hardware setup to point to USB Blaster I/II. 

4. Perform “auto-detect” to detect the physical device in the JTAG chain. 

5. Right click on the detected Cyclone V device and choose “change file” 

6. Browse to the generated .jic and click ok. 

7. Tick on “Program/Configure”. 

Note: The programmer will automatically add “factory default enhanced SFL image” to configure the device so that a bridge will be formed between the JTAG port and the ASMI. 


8. Click start to begin the programming process. 

9. You should see the design running on the development kit after a power cycle/pulsing the nCONFIG pin.

Fast Passive Parallel (FPP) Configuration Mode

Theory

FPP is another configuration scheme where the FPGA device is configured with configuration data stored in external flash. In this scheme, the configuration process is controlled by an external host/microprocessor hence it is known as a passive type of configuration scheme. This allows the microprocessor to change the target FPGA device’s functionality while the system is in operation by reconfiguring it. This scheme is considered the fastest among all the configuration schemes as the data transfer occurs over several data lines (8-, 16- and 32-bits data width) which in turns leads to shorter programming time. The figure below gives a general idea on the relationship of the microprocessor, external flash and the FPGA: 

Note: Image taken from Cyclone V handbook. Other devices might require the resistors to be pulled up to different VCC. Please refer to the respective handbook/Pin connection guideline.

Altera provides Parallel Flash Loader (PFL) IP core that is able to program and control FPGA configuration with data from external flash. This walkthrough will focus on the PFL IP’s implementation in Altera’s CPLD which will act as the “brain” to control the configuration process.

Parallel Flash Loader (PFL) IP Core

PFL IP core when instantiated in Altera’s CPLD is capable of programming Common Flash Interface(CFI) flash, quad Serial Peripheral Interface (SPI) flash or NAND flash memory devices via the device JTAG interface. It then controls the FPGA configuration process by facilitating the data transfer process from either one of the flash formats stated above. Below are two figures that show the programming and configuration process respectively. 

Note: 

- You can use the PFL IP core to either program the flash memory, configure your FPGA or both at the expense of more logic elements(LE). 

- For more in depth explanation of the PFL IP core, please refer to the user guide: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_pfl.pdf

Hands-On with Fast Passive Parallel Configuration

As this configuration scheme requires a microprocessor, this hands-on section will be split into two parts, the first part is a guide on how to instantiate and connect the PFL IP core in an Altera CPLD (MAX V) and the second part will describe the design and setting required from the FPGA part.

Required hardware & software

Hardware: Cyclone V GX development kit 

Software: Quartus Prime 16.0

Quartus MAX V Design & Settings

1. This is a simple PFL design:File:PFL MV.qar. Copy and paste this .qar into your project directory. Restore this design by going to Project → Restore Archived Project. 

2. Pin assignments are performed in Assignment → Pin Planner. Refer to development kit reference manual for information on pin location if you wish to change pin assignments. 

3. Go to Assignment → Device → Device & pin options → Unused Pins. Ensure that the unused pins are reserved as input tri-stated. 


4. You can check the settings in the PFL IP core by going to Tools  Qsys and open PFL.qsys.

Note: 

- FPP x 16 is chosen as the development kit’s default MSEL pins setting support FPP x 16. 

- This option bit holds the addressing information of the configuration data stored in the CFI flash. 18000(in hex) is chosen as the CFI flash has been preprogrammed with the option bit stored at 18000. CFI flash memory map obtained from the user guide of the development kit:


5. Compile the design by going to Processing → Start Compilation to obtain the .pof

1/1e/16.png

d/d6/15.png

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