Configuring the Transceiver Reconfiguration Controller and the PCIe Reconfig Driver for Stratix V and Arria V GZ PCIe Hard IP Designs
When designing a PCIe component for Stratix V or Arria V GZ in Qsys, three components are needed to be instantiated. They are Hard IP for PCIe, Transceiver Reconfiguration Controller, and Altera PCIe Reconfig Driver.
The Hard PCIe IP - Acts as a bridge between the PCIe domain and the user application domain.
The Transceiver Reconfiguration - Controller is used to do the calibration for the transceivers.
The PCIe Reconfig Driver - It fine tunes the transceivers and optimizes them.
Since the Transceiver Reconfiguration Controller is not just used for PCIe and can be used for other high speed serial IPs, so not all features are needed. Similar situation applies to the Reconfig Driver as well. This page shows which parameter options must be selected in the Transceiver Reconfiguration Controller and PCIe Reconfig Driver for different PCIe speeds. Note for Gen1 the Reconfig Driver is NOT needed.
Enter a value into "Number of reconfiguration interfaces" base on the link width. The value shown in the Figure 2 below is for a x8 link. For the values of other configurations, please refer the Figure 8 at the end of the page, it lists out the values for all configurations.
Do not enable any option. All the rest are not needed for PCIe Gen1 speed and they may worsen the signal integrity if they are enabled.
Enter a value into the field "Number of reconfiguration interface" base on the link width. The value shown in Figure 4 below is for a x8 link. Refer the Figure 8 at the end of the page for other configurations.
Enter a number into the field of "Number of reconfiguration interfaces" base on the link width. The number shown in Figure 6 below is for a x8 link. Refer the Figure 8 at the end of the page for other configurations.
Enable the option "Enable adaptive equalization (AEQ) block" as shown in Figure 5 below. AEQ is a must for PCIe Gen3 speed.
Number of Reconfiguration Interfaces for different PCIe link width and speed
Figure 8 lists out the needed number of reconfiguration interfaces for different PCIe link width and speed. It is native width and speed when configure the hard PCIe IP in Quartus, not the negotiated width and speed after link training.
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