Qsys Pro has a new Generic Component type that allows you to quickly create Blackbox, HDL or custom IP components. These components can later be exported as IPXACT or _hw_tcl formats for use in other Qsys projects. Qsys Pro also allows the port types of existing components to be modified. This document and the example project shows several examples of creating these components in Qsys Pro. The zip file contains the Qsys project files.
The Altera IOPLL (io_pll_0) component was modified to redefine the lock signal output to a Reset Output. This signal is then used as one of the reset inputs to a reset controller component. This is useful when you would like to hold logic in reset until the PLL locks. After making this change, you will notice a warning if you click the Validate System Integrity button. This is because the function for this lock signal no longer matches the signal type in the ip file.Modifying the port type of a component
A Generic component (custom_logic_bb) was created as a black box component and hooked up to a FIFO component. This black box component represents the interface for a user module that will later contain RTL. The black box component allows the interface to be defined and hooked up to the rest of the components in the Qsys system and prevent the logic from being synthesized away. This component has an Avalon Streaming sink interface defined and is hooked up to the FIFO. This was created by mirroring the AVST interface of the FIFO. There is also a conduit that contains custom signals that is exported to be hooked to other user logic at the top level. The Avalon MM slave interface is a placeholder for the host control interface. The component can later be changed to an HDL type component once the RTL is ready.
The DDR_subsystem is an example of using a separate Qsys project as a submodule. These small Qsys systems are good for design blocks that are used in multiple projects. This subsystem has a ddr4 external memory interface module that is hooked up to a black box. This allows the ddr4 pins to be exported to the top level where they can be quickly assigned using the Blueprint tool. The black box component hooks up the Status conduit and Avalon MM interface to the memory controller to prevent logic from being optimized away. The black box interface can be quickly created by using the clone and mirror functions to define the ports. The clone was used for the status conduit and the mirror was used to create the Avalon MM Master interface.
The csr_slave component was created from an existing HDL file. This allows users to take their HDL module and quickly define Qsys port types to hook up within their Qsys system. The HDL file was analyzed to create the ports of the Qsys component. This component has an Avalon memory map slave interface. The signal names were mapped to the Avalon MM function in the Signal & Interfaces tab. The component also has a conduit that contains status and general purpose output signals that are exported.
This component can be used in other Qsys systems by exporting it to create a _hw.tcl file or an IP-XACT file. These exported files can then be added to the Qsys library for use in other Qsys systems.
The slave_burst_0 component was created as a generic component with an Avalon MM slave burst interface. The component was exported to create the hw_tcl file. The hw_tcl file was then edited to add parameters for the data, address and burst widths. These widths can be set in the Parameter window for each individual instance of the component.
It is often helpful to create a custom layout in Qsys to quickly change views. A separate view for parameterizing components or hooking up components is useful. You can create custom layouts in the View-Custom Layouts menu. These custom layouts are persistent on your local computer and can be used in other Qsys projects. You can also export the custom views and then import them on a different computer.
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