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Crete3 Demo Designs

Crete3 Demo Designs



Script with useful procedures for use in system console for Stratix 10 TX E-tileCrete3 Demo Designs

  • Updated (02/10/2018)

        0/04/Ttk_helper_s10tx.tcl V1.7 (02/10/2018) 


Library of C-functions for E-tile transceivers using AVMM Interface

  • Functions for configuring PMA settings, adaptation etc. (These are the same functions as used in the 60 Channel Hard PRBS PAM4 design) :

         2/29/PMA_functions_ETILE.c (09/10/2018) 

         1/17/PMA_functions_ETILE.h  (09/10/2018) 


Dynamic Reconfiguration

  • Updated (29/10/2018) Stratix 10 TX SI Board (S1): 2 channel PAM4/NRZ 58 Gbps soft PRBS test design connected to SMA_A and SMA_B (allows to reconfigure datarate as well as encoding (PAM4/NRZ) dynamically on tranmit and receive seperately)

         7/7a/Prbs_2ch_ETILE_58Gbps_PAM4_SMA.zip (18.1 B222) 



Superlite IV

  • NEW (17/10/2018) Stratix 10 TX SI Board (S1) : Superlite IV Demo design using 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 100 Gbps of raw data

        2/2c/S10TX_SIBoard_SuperliteIV_Etile_2x2_lanes_53Gbps_dual_QSFP.zip (18.1 B222) 


Superlite II

  • NEW (05/11/2018) Stratix 10 TX SI Board (S1) : Superlite II V4 Demo design using 2 times 4 lanes at 28.3 Gbps to transport 110 Gbps of raw data

        2/24/S10TX_SIBoard_SuperliteII_V4_Etile_2x4_lanes_28Gbps_dual_QSFP.zip (18.1 B222) 



KP FEC

  • NEW (14/09/2018) Stratix 10 TX SI Board (S1): Dual Phy with each 2 channels PAM4 soft PRBS demo design using Etile HIP in FlexE mode and KP-FEC, net datathroughput 100 Gbps (to test with DAC cable)

         5/54/Prbs_2x2ch_ETILE_53Gbps_KPFEC_qsfp_1x2.zip (18.1 B209) 


  • NEW (07/09/2018) Stratix 10 TX SI Board (S1): 2 channel PAM4 soft PRBS demo design using Etile HIP in FlexE mode and KP-FEC, net datathroughput 100 Gbps

         c/c0/Prbs_2ch_ETILE_53Gbps_KPFEC_qsfp_1x1.zip (18.1 B208) 


Ultralite II

  • (19/07/2018) Stratix 10 TX SI Board: 400G Ultralite II V2 demo design with auto-training using 16 lanes at 25.8 Gbps routed to the 1x2 QSFP-DD modules

        b/b8/S10TX_SIBoard_UltraliteII_V2_Etile_400G_16_lanes_26Gbps_QSFP_DD.zip (18.0.1 B261) 


  • (19/07/2018) Stratix 10 TX SI Board: 100G+ Ultralite II V2 demo design with auto-training using 8 lanes at 30 Gbps routed to the 1x2 QSFP-DD modules

         f/fb/S10TX_SIBoard_UltraliteII_V2_Etile_8_lanes_30Gbps_QSFP_DD.zip(18.0.1 B261) 


Hard PRBS Test Designs

  • Updated (09/10/2018) Stratix 10 TX SI Board (S1) : 60 channel PAM4/NRZ Design at 57.8 Gbps with Internal noise (allows to reconfigure from PAM4 to NRZ dynamically)

        7/74/Nios_remove.zip (18.1 B222) 


  • Updated (21/08/2018) Stratix 10 TX SI Board: 48 channel PAM4/NRZ Design at 57.8 Gbps with Internal noise (allows to reconfigure from PAM4 to NRZ dynamically)

       3/33/Nios_48ch_E_TILE_PAM4_58Gbps.zip(18.0.1 B261) 


  • Updated (10/10/2018) Stratix 10 TX SI Board (S1) : 120 channel Dual Mode (NRZ/PAM4) at 28.3 Gbps with Internal noise (Requires updated regulator settings to run all channels > 25 Gbps)

        5/52/Nios_120ch_E_TILE_dual_mode.zip (18.1 B222) 


  • Updated (30/08/2018) Stratix 10 TX SI Board: 96 channel Dual Mode (NRZ/PAM4) at 30 Gbps with Internal noise

        d/d9/Nios_96ch_E_TILE_dual_mode.zip (18.0.1 B261) 


  • (17/05/2018) Stratix 10 TX SI Board: 24 channel Dual Mode (NRZ/PAM4) at 30 Gbps

         2/29/Nios_24ch_E_TILE_dual_mode.zip (18.0 B219) 


  • (17/05/2018) Stratix 10 TX SI Board: 12 Channel PAM4 High Datarate (57.8 Gbps)

         a/a1/Nios_12ch_E_TILE_PAM4_58Gbps.zip (18.0 B219) 


Soft PRBS Test Designs

  • (28/06/2018) Stratix 10 TX SI Board: 2 channel NRZ/PAM4 30 Gbps soft PRBS test design connected to SMA_A and SMA_B

         e/e7/Prbs_2ch_ETILE_30Gbps_dual_mode_SMA.zip (18.0 B219) 


  • Updated (12/07/2018) Stratix 10 TX SI Board: 8 Channel Soft PRBS 30 Gbps Dual Mode connected to QSFP-DD 1x2 Module

         c/c3/Prbs_2x4ch_ETILE_30Gbps_dual_mode_qsfp_1x2.zip (18.0.1 B261) 


  • Updated (22/05/2018) Stratix 10 TX SI Board: 4 channel PAM4 58 Gbps soft PRBS test design connected to QSFP-DD 1x2 Module

         7/7a/Prbs_2x2ch_ETILE_58Gbps_PAM4_qsfp_1x2.zip (18.0 B219) 

Version history
Last update:
‎06-25-2019 03:39 PM
Updated by:
Contributors