CvP Example Designs for Arria 10 GX FPGA Development Kit

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CvP Example Designs for Arria 10 GX FPGA Development Kit

Description

This is an example design of CvP for Arria 10 GX FPGA Development Kit. 

• FPGA Designs
• PCIe Gen2 x8 Avalon-MM 256bit CvP Initialization mode

The periphery configuration scheme is ASx4.

These designs include Conversion Setup File (.cof) and tcl file for Convert Programming Files during full compilation.

• USER LED
• USER_LED_G0 : L0 State
• USER_LED_G1 : Alive (Blinking after core configuration)
• USER_LED_R3 : PCIe Gen2
• USER_LED_R4 : PCIe Gen3
• USER_LED_G5 : Lane x1
• USER_LED_G6 : Lane x4
• USER_LED_G7 : Lane x8

• Hardware Setup

1. Set factory Default except for SW5.1 and SW5.2
2. Set SW5.1 to "ON" and SW5.2 to "OFF" to set AS configuration mode (MSEL[2:0]=3'b010)
3. Program EPCQ-L1024 with a10_g2x8_avm_cvp.periph.jic
4. Install the development kit to you PC

• CvP Procedure

1. Power up your PC
2. Open a command prompt window
3. Execute the following command
4. quartus_cvp --vid=1172 --did=e003 a10_g2x8_avm_cvp.core.rbf

Content

• Project
• 9/90/A10_g2x8_avm_cvp_151.qar