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Cyclone® V SoC - Access to Si570 via I2C using MAX V

Cyclone® V SoC - Access to Si570 via I2C using MAX V



Description

This wiki page is dedicated towards users that would like an example using:

  • Cyclone V SoV Development Kit
  • Modifying frequencies of on-board oscillators
  • Qsys
  • On-board MAX V
  • System Console

This entry was initiated due to the fact that the 'Board-Test-Software' (BTS) for this development kit did not work with the newest Quartus Prime version (V17.0) and/or the used Windows 10.

The purpose of this solution is to get access to the internal I2C bus which is connected to several 'SiLab' oscillators. The frequencies of these devices can be changed by using their I2C interface.

Unfortunately this I2C bus is not accessible from outside. The bus is connected to the MAX V devices witch acts as a system controller. But since then BTS uses also only the JTAG interface to control

different hardware resources of the board there should be a way to get control of the I2C bus too.

MAX V Controller

The JTAG interface either by using the internal or an external USB-Blaster is connected to three devices: MAX V, HPS and the FPGA. For the following example the JTAG port of the MAX V is used.

The design for the MAX V is available as HDL code. After installing the Kit Installation(EXE) package, the source can be found in the subdirectory: C:\altera\14.1\kits\cycloneVSX_5csxfc6df31_soc\examples\max5.

The file system_max_RevE1.zip contains all project files. The most interesting part here is the Qsys file. The system consists of five parts:

  • Clock Source
  • System_max_ID
  • vj_avalon_master
  • i2C_cont_bridge
  • OpenCores I2C

The following picture show the system in Qsys:

Cyclone® V SoC - Access to Si570 via I2C using MAX V Qsys.png


For the I2C interface the IP core from 'OpenCores' is used. The "i2c_cont_bridge" acts as an interface between the virtual JTAG controller "vj_avalon_master" and the I2C core.

Beside of an address mapping this core also handles the complete protcol required by the I2C core. An access (read or write) from the JTAG interface is automatically (via FSM) mapped into complete sequence of commands send to the I2C core.

In this way data from the JTAG core is transferred to and from the I2C devices. The "vj_avalon_master" implements an additional "sld_virtual_jtag" instance which connects to the JTAG hub and the external world.

SLD Virtual JTAG

The "vj_avalon_master" implements a "SDL_Virtual_JTAG" (System-Level-Debugging) interface which connect to the JTAG hub. This core extends the IR-/DR-Register of the device JTAG chain.

Version history
Revision #:
1 of 1
Last update:
‎06-25-2019 04:32 PM
Updated by:
 
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