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Cyclone V Transceiver PHY Basic Design Examples

Cyclone V Transceiver PHY Basic Design Examples



Cyclone V Custom PHY with automatic synchronization state machine design example

Overview

This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Custom PHY with automatic synchronization state machine. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers. The design consist of only one transceiver channel with data pattern switch between synchronization and incremental pattern. The design also come with example test bench and TCL file to run simulation in Modelsim for reference.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Cyclone V Custom PHY with automatic synchronization state machine design example QII v15.0 (ZIP)       

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceCyclone V GX
Quartus versionQuartusII v15.0
Modelsim versionModelSim ALTERA STARTER EDITION 10.3d
Datarate1Gbps
Data patternFixed and incremental
Number of channels1
IP usedCustom PHY IP, Transceiver Reconfiguration Controller

Cyclone V Native PHY with manual alignment design example

Overview

This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with manual alignment. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers. The design consist of only one transceiver channel with data pattern switch between synchronization and incremental pattern. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. Note that you should create your own word aligment controller as the control is done in test bench in the example.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Cyclone V Native PHY with manual alignment design example QII v15.0 (ZIP)

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceCyclone V GX
Quartus versionQuartusII v15.0
Modelsim versionModelSim ALTERA STARTER EDITION 10.3d
Datarate1Gbps
Data patternFixed and incremental
Number of channels1
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller

Cyclone V Native PHY with bit slip alignment design example

Overview

This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with bit slip alignment. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers. The design consist of only one transceiver channel with fixed synchronization pattern. Note the bit slip controller is just for reference only. You should create your own bit slip controller. The design also come with example test bench and TCL file to run simulation in Modelsim for reference.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Cyclone V Native PHY with bit slip alignment design example QII v15.0 (ZIP) 

  

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceCyclone V GX
Quartus versionQuartusII v15.0
Modelsim versionModelSim ALTERA STARTER EDITION 10.3d
Datarate1Gbps
Data patternFixed
Number of channels1
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller

Cyclone V Native PHY with manual alignment and byte ordering in single width mode design example

Overview

This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with manual alignment and byte ordering in single-width mode. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The design consist of only one transceiver channel with fixed 16 bits data pattern. In the test bench, the MSByte and LSByte of the data pattern are purposely swapped half way during simulation to show the byte ordering occurence in case the correct byte ordering has been achieved directly after word alignment. Note that you should create your word alignment and byte ordering controller as the controls are done in test bench in the example.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Cyclone V Native PHY with manual alignment and byte ordering design example QII v15.0 (ZIP)   

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceCyclone V GX
Quartus versionQuartusII v15.0
Modelsim versionModelSim ALTERA STARTER EDITION 10.3d
Datarate1Gbps
Data patternFixed
Number of channels1
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller

Cyclone V Native PHY with manual alignment and byte ordering in double width mode design example

Overview

This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with manual alignment and byte ordering in double-width mode. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The design consist of only one transceiver channel with fixed 32 bits data pattern. In the test bench, the MSByte and LSByte of the data pattern are purposely swapped half way during simulation to show the byte ordering occurence in case the correct byte ordering has been achieved directly after word alignment. Note that you should create your word alignment and byte ordering controller as the controls are done in test bench in the example.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Cyclone V Native PHY with manual alignment and byte ordering design example QII v15.0 (ZIP)    

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceCyclone V GX
Quartus versionQuartusII v15.0
Modelsim versionModelSim ALTERA STARTER EDITION 10.3d
Datarate1Gbps
Data patternFixed
Number of channels1
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller

Cyclone V Native PHY with manual alignment, 8b10b enabled and byte ordering in single width mode design example

Overview

This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with manual alignment, 8b10b enabled and byte ordering in single width mode. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The design consist of only one transceiver channel with fixed 16 bits data pattern. In the test bench, the MSByte and LSByte of the data pattern are purposely swapped half way during simulation to show the byte ordering occurrence in case the correct byte ordering has been achieved directly after word alignment. Note that you should create your word alignment and byte ordering controller as the controls are done in test bench in the example.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Cyclone V Native PHY with manual alignment, 8b10b enabled and byte ordering in single width mode des... (ZIP)

Version history
Revision #:
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Last update:
‎06-25-2019 04:29 PM
Updated by:
 
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