Showing results for 
Search instead for 
Did you mean: 
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

DCFIFO with ALTECC Implementation Example Design

DCFIFO with ALTECC Implementation Example Design




This design example uses an DCFIFO to illustrate how the ECC feature can be implemented external to the FIFO. The ALTECC_ENCODER and ALTECC_DECODER IP cores are required as the ALTECC_ENCODER IP core encodes the data input before writing the data into the DCFIFO, while the ALTECC_DECODER IP core decodes the data output from the DCFIFO before transferring the data out to other parts of the logic.


The example design and the details description of the design can be downloaded from the following links.


File:DCFIFO with ALTECC Implementation Example Design.pdf

System Requirements

Quartus II version 14.1


This design example describes how ECC features can be implemented with the DCFIFO using ALTECC. However, the design example might not represent the optimized design or implementation.

Version history
Last update:
‎06-25-2019 04:35 PM
Updated by: