The DDR memory half-rate bridge component available in SOPC Builder version 8.1 is used to perform half-rate memory accesses with reduced read latency. Instead of using the DDR2-SDRAM memory controller in half-rate mode, you can use the half-rate bridge in conjunction with the full-rate memory controller. The half-rate bridge component performs a 1:2 clock crossing between a master and the memory controller but only adds two cycles of latency versus the typical eight cycles introduced when using the memory controller half-rate mode.
You are free to use this design in any way you like. If you want to contibute to this project feel free to do so. I'm providing this design as is and Altera will not be supporting it. To avoid the need to use this bridge you can upgrade to Quartus II version 9.1 where the memory controller has the option to have this bridge built in.