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DDR Memory Half-Rate Bridge

DDR Memory Half-Rate Bridge


The DDR memory half-rate bridge component available in SOPC Builder version 8.1 is used to perform half-rate memory accesses with reduced read latency. Instead of using the DDR2-SDRAM memory controller in half-rate mode, you can use the half-rate bridge in conjunction with the full-rate memory controller. The half-rate bridge component performs a 1:2 clock crossing between a master and the memory controller but only adds two cycles of latency versus the typical eight cycles introduced when using the memory controller half-rate mode.

To use the supplied design example, you will need a Cyclone® III FPGA development kit and the Quartus® II design software version 8.1.

Design Specification

  • Nios® II/f core
  • Level-1 JTAG debug module
  • DDR memory half-rate bridge
  • Pipelined bridge
  • System timer
  • Tightly coupled memory
  • System-ID peripheral

Figure 1. DDR Memory Half-Rate Bridge Example


  1. TCDM: Tightly coupled data master
  2. TCIM: Tightly coupled instruction master
  3. M: Master
  4. S: Slave



You are free to use this design in any way you like. If you want to contibute to this project feel free to do so. I'm providing this design as is and Altera will not be supporting it. To avoid the need to use this bridge you can upgrade to Quartus II version 9.1 where the memory controller has the option to have this bridge built in.

Version history
Last update:
‎06-25-2019 04:42 PM
Updated by: