DDR Timing with TimeQuest
Disclaimer
The attached document ("DDR_Timing_Cookbook.pdf") is intended to provide guidance on how to constrain double-data rate interfaces in Altera FPGAs when Timing Constraints are not provided for you. For Altera’s double data rate memory controller IP, as an example, timing constraints are provided for you, and those scripts should always be used.
File:DDR Timing Cookbook.pdf
File:DDR Timing Cookbook designs.zip
This material was written to complement the Altera training classes available through www.altera.com.
The Quartus II Software Design Series: Timing Analysis
http://www.altera.com/education/training/courses/IDSW120
Advanced Timing Analysis with TimeQuest
http://www.altera.com/education/training/courses/IDSW125
The text provides TimeQuest commands to constrain a specific design referred to in the document. Please be advised that these constraints will very likely need to be modified to work with your own design. Do not attempt to constrain your design without thoroughly understanding its configuration, and please do not attempt to copy and paste these commands directly, expecting them to work right off the bat. You must understand your design and make appropriate modifications to these constraints in order to be assured of success.
Furthermore, these design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
--
Additional Information
This document refers to the 16 reference design variants in the zip file:
"DDR_Timing_Cookbook.zip", also located on the AlteraWiki.
The designs allow you to explore different DDR input and output configurations for practice. The designs are labeled according to the configuration employed. For instance: the nomenclature "DDR_CESO" signifies that the DDR reference design has (C)enter-aligned clock-data at the inputs, (E)dge-aligned clock-data at the outputs, with (S)ame-edge data transitions on the inputs, and (O)pposite-edge transitions on the outputs.
Please take time to thoroughly understand the configuration of your own design before attempting to copy and paste any constraints from these reference designs. They will most likely need to be modified to suit your own design. Again, Altera provides DDR timing scripts for our DDR memory IP as well as other IP cores. When you are provided with such timing scripts, please use the them as per the guidelines established in the documentation for the IP in lieu of the information provided here.
