Reference designs below use VHDL. All designs below use the latest (12.0 suite) version of Quartus, ModelSim-Altera (starter-edition), Qsys and NIOS II SBT for Eclipse. Note that to use DSP Builder, you need Quartus subscription edition.
VGA Interface. This VGA interface has both a VHDL and a NIOS based design. The NIOS based design is more interesting since it demonstrates the Altera University Program Qsys cores and the use of a timer interrupt to display system up-time on a VGA monitor.