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DSP block 8 tap FIR

DSP block 8 tap FIR

The following is a how to document describing the process to build an 8 tap FIR filter using DSP blocks. There are a couple of things to note when using Altera Stratix III, Stratix IV, or Arria II device DSP blocks to build a high performance, fully parallel FIR filter.

ALTMULT_ADD for coefficients 1-4

  1. First, create an ALTMULT_ADD megafunction in the MegaWizard under Arithmetic for the first 4 filter coefficients. The number of multipliers should be set to 4. Rounding and saturation will only be applied after accumulation, so it will not be enabled in the DSP block for the first 4 coefficients. Both bus A and B should be set to 18 bits with signed representation, and the result width should be set to 44 bits even though the maximum number of bits required by the 4-MAC function is 38 bits. The result width must be set to 44 bits in order to enable the chainout function used to cascade DSP blocks
  2. On the next tab, Extra Modes, the Register output of the adder unit checkbox should be checked to maximize performance. The Use dedicated multiplier circuitry radio button should be selected #On the Chainout/Shift/Loopback tab, the chainout adder should be enabled. Enabling the chainout adder is required to cascade the DSP blocks. To pipeline for performance, the Register output of the chainout adder unit box should be checked
  3. The Saturation and Rounding tabs will not have any selectable options since hardware support was not enabled on the General tab
  4. On the Multipliers tab, both multiplier input registers should be enabled in addition to the multiplier output register. The design is fully pipelined to maximize performance
  5. On the EDA tab, you can see that the altera_mf library is required for simulation of altmult_add in 3rd party tools. On the Summary tab, files for instantation of the altmult_add megafunction can be enabled

ALTMULT_ADD for coefficients 5-8

The 2nd ALTMULT_ADD megafunction will have different settings since it will need to accept input from another DSP block, and will feature saturation and rounding. The ALTMULT_ADD should be configured with 4 18 x 18 bit signed multipliers with a 44 bit wide output. Support for hardware saturation and rounding should be enabled

  1. In Extra Modes, the adder unit should be registered, and the dedicated multiplier circuitry should be selected
  2. On the Chainout/Shift/Loopback tab, the chainout adder must be enabled because the DSP blocks are cascaded. The chainin input must also be enabled

To do:

  • Pick coefficients
  • Finish altmult_add coefficients 5-8 settings
  • Show schematic of system without compensation register
  • Show simulation without compensation register
  • Show schematic of final system with compensation register
  • Show simulation with compensation register
  • Convert design to HDL?
  • Upload design?

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Version history
Last update:
‎06-25-2019 11:07 PM
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