Simulink test-bench - that is blocks to provide inputs, and to analyse inputs and outputs
Required DSPBA top level parameterization blocks: Signals (bus clock specification, system clock specification) & Control (RTL output directory, top level threshold parameters)
Links to open post-generation tools: Run Modelsim (open ModelSim to run generated RTL testbench and compare against Simulink at the synthesizable system level), Run Quartus (open the generated RTL project in Quartus to do a full Quartus compile)
Other blocks, such as: Run All Testbenches - a UI for the scripts to control run system-level and ModelIP and primitive subsystem level Automatic Test Benches (ATBs), optional short-cuts to edit parameterization files that run on model start-up and/or pre- or post-simulation
The part of the design to be synthesized is separated hierarchically. What will form the top level of the synthesizable part is indicated by a Device block, which sets which family, part, speed grade etc to target.
This level can consist of further level of hierarchies that include 'Primitive Subsystems' - scheduled domains for ModelPrim blocks (alternatively referred to as 'primitive' blocks; the low-level blocks such as delays, mults, adds) - and ModelIP Blocks - the standalone macro functions (NCO, FIR, CIC)
Optionally further LocalThreshold blocks can be included to override threshold settings defined higher up the hierarchy
Primitive Subsystems are scheduled domains for the ModelPrim ('primitive') blocks. A SynthesisInfo block is required with synthesis style set to 'Scheduled' (allowing the tool to pipeline and redistribute memories optimally to acheive the desired clock frequency). Boundary blocks that delimit the primitive subsystem are also required: ChannelIn (Channelized Input), ChannelOut (Channelized Output), GPIn (General Purpose Input) and GPOut (General Purpose Output). Within these boundary blocks the tool will optimize the implementation specified by the schematic - including the insertion of pipelining registers required to achieve the specified system clock rate. When inserting pipelining registers, equivalent latency has to be added to parallel signals that are required to be kept synchronous so that they are scheduled together. Signals that go through the same input boundary block (ChannelIn or GPIn) are scheduled to start at the same point in time; Signals that go through the same output boundary block (ChannelOut or GPOut) are scheduled to finish at the same point in time. Any pipelining latency added to achieve Fmax is then added in balanced 'cuts' through the signals across the design. The correction to the simulation to account for this latency added in HDL generation is applied at the boundary blocks, such that the Primitive Subsystem as a whole will remain cycle accurate.
Note that further levels of hierarchy can be defined within primitive subsystems containing primitive blocks - (but no primitive boundary blocks or ModelIP blocks)
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.