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Design Example - 10GBase-R (Stratix V GX)

Design Example - 10GBase-R (Stratix V GX)



Overview

This article covers the steps required to succesfully instantiate the reference design for the Physical Coding SUblayer (PCS) for the 10GBase-R protocol on a Stratix V FPGA (For Quartus II v11.0 or v12.0sp1 or v13.1). The goal of the article is to briefly guide the user through the design, compilation, and simulation of the Altera generated PIPE reference design. After finishing the article, the reader will be able to:

  • Identify major functional blocks within the design
  • Understand at a high level the operation of the Altera generated 10GBase-R example
  • Compile the reference design in Quartus and ModelSim
  • Simulate the design in ModelSim

This guide assumes the reader has standard knowledge of the use of Quartus and ModelSim.


External Links 

Altera Transceiver PHY IP Core User Guide (PDF) - This document describes configuration details for the 10GBase-R PHY IP (Useful when generating the IP from the MegaWizard)

Altera Stratix V Device Documentation - Transceiver Architecture, Clocking, Configurations and reset controller information.

Altera Avalon Memory-Mapped Interface Specification (PDF) - Avalon Mmemory-Mapped Interface Protocol information. 

ModelSim SE Command Reference (PDF) - A guide to tcl commands and in ModelSim.


Design File

  • for v11.0 or 12.0sp1

Altera 10GBase-R Design File (ZIP) 

  • for v13.1

Altera 10GBase-R Design File v13.1 (ZIP); 


Note: v13.1 design file is created by regenerating all the megafunction files of the older Quartus version by selecting tools -> Megafunction Plug-In Manager -> Edit a custom megafunction variation -> next -> selecting 1 file at a time -> next -> check if all parameter values are same as older megafunction -> finish. 

After the new files are regenerated remove the older files from the project and add the newly generated files to the project.


Design Specifications

The table below lists the specifications for the design: &nbsp with QuartusII version 11.0;

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v11.0, b157
Modelsim versionModelsim SE v6.6d
Datarate10.3125Gbps
Data patternXGMII data
Number of channels1
IP used10GBase-R PHY IP, Traceiver Reconfiguration Controller

  

The table below lists the specifications for the design: &nbsp with QuartusII version 13.1;

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v13.1
Modelsim versionModelsim SE v10.0d
Datarate10.3125Gbps
Data patternXGMII data
Number of channels1
IP used10GBase-R PHY IP, Traceiver Reconfiguration Controller

 

Design Overview

The Top Level components that must be instantiated within the top.v file are:

top_10GbaseR (Altera Generated through the MegaWizard)

mgmt_master  (Altera Generated through the MegaWizard) 

xgmii_src        (User Generated) 

xgmii_sink     (User Generated) 

top_reconfig   (User Generated) 

top                  (User Generated)

top_tb             (User Generated)


Please see figure 1-1 


Figure 1-1: Top Level Block Diagram of the Reference Design Example for 10GBase-R on a Stratix V Device

d/d9/10GbaseR_Top_Level_Block_Diagram.jpeg ( 10GbaseR Top Level Block Diagram.jpeg - click here to view image )


Top_10GBaseR


Compilation in Quartus

  1. Open the project file (.qpf) by going to File > Open Project and navigating to <project_directory>\10GBASER_checkout_mif_A7. Open top.qpf.
  2. Before compiling you must regenerate the Altera generated IP using the Megawizard. Perform the following steps for however many altera generated IPs there are in the design. Go to Tools > Megawizard Plugin Manager. Once the dialogue box opens up, select "edit an exisitng custom megafunction variation." select the file you want to generate (there will be several .v files to choose from, and you will need to complete this process for each of them). Then click next. After a few moments another dialogue box will appear. Here you will be able to customize the Altera generated IP. After you have selected your options, click Finish and the file will be generated.
  3. After the previous steps have been completed, you can compile the entire design by going to Processing > Start Compilation.
  4. You can expect following critical warnings during compilation.
  • Memory depth (8) in the design file differs from memory depth (6) in the Memory Initialization.
  • Memory depth (8) in the design file differs from memory depth (6) in the Memory Initialization.
  • No exact pin location assignment(s) for 12 pins of 12 total pins
  • Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • Timing requirements not met


Compilation in ModelSim

You will need to create a .tcl script called phy_sim_top.tcl (there already exists a phy_sim_top.tcl in the zip that contains the project files, however you will need to modify it if you add your own design files) that contains compilation commands for:

  1. Stratix V Library files
  2. PHY top_10gbaser Instance files
  3. Reconfig Controller instance files
  4. User created design files
  5. The Top Level Testbench file
  6. Commands to ivoke the simulator


  • make sure that the QUARTUS_ROOTDIR variable is set correctly in phy_sim_top.tcl. Note: the set QUARTUS_ROOTDIR $env(QUARTUS_ROOTIDIR) line sets the variable to the local systems version of quartus. To be safe, use set QUARTUS_ROOTDIR <your_quartus_root_directory>.
  • It is important that the files in the .tcl be ordered as they are ordered in the plain_files.txt included in the zip file. The directory of theplain_files.txt is (<project_directory>\10GBASER_checkout_mif_A7\top_10GbaseR_sim\altera_xcvr_10gbaser) for thetop_10gbaser instance files, and (<project_directory>\10GBASER_checkout_mif_A7\top_reconfig_sim\alt_xcvr_reconfig) for the reconfig_controller files.


All Altera generated IP needs its own library. Use thevlib <directory_name> command to create a design library. Use the following Tcl code as a reference:

vlib msim_top_10GbaseR => creates a design library called msim_top_10GbaseR in the current working directory.

Note that for ModelSim compilation, a vlog of the files is required before the vsim command. Use the vlog command to compile Verilog source code into a specified working library (or to the work library by default).

For example: vlog -work msim_top_10GbaseR test.v => compiles the test.v file into the msim_top_10GbaseR directory.

The -work <library_name> Specifies a logical name or pathname of a library that is to be mapped to the logical library work. By default, the compiled design units are added to the work library. If a pathname is specified, the specified pathname overrides the pathname specified for work in the project file.

If compiling a System Verilog file (.sv), you must place the "-sv" command after the "vlog" command and before the name of the file to be compiled.

After writing commands to create necessary libraries and compile design units, use the vsim command to invoke the modelsim simulator. Use the-c option to run the simulation in command line mode. The-novopt turns off the optimizations for vcom, vlog and vsim commands while using Modelsim SE only. The-t <number> sets the time scale to <number>.

Use this example script as a reference, and see this guide for a reference to using tcl commands in ModelSim. 


Simulation Guidelines

The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl 


Update History

  1. Initial Release - May 05 2011 


 See Also

  1.  Transceiver design examples 

 

Key Words

Stratix V, 10GBase-R PHY IP, Tranceiver Reconfiguration Controller 


   

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misleading or inaccurate.Retrieved from http://www.alterawiki.com/wiki/Altera_Wiki

 

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