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Design Example - Arria II GX DDR2 SDRAM ALTMEMPHY 267MHz x64

Design Example - Arria II GX DDR2 SDRAM ALTMEMPHY 267MHz x64

Last Major Update

Initial Release – January 2010 – Arria II GX DDR2 SDRAM x64 267MHz, Quartus II v9.1, DDR2 SDRAM High Performance Controller II with ALTMEMPHY, Arria II GX Development Kit.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR2 SDRAM interface working with a Arria II GX FPGA using a single Micron MT8HTF12864HDY-800G1 DDR2 SDRAM SODIMM on the Arria II GX Development Kit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the ALTMEMPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process.

The lab creates a 64 bit 267MHz DDR2 SDRAM external memory PHY and controller using Altera’s DDR2 SDRAM High Performance Controller II with ALTMEMPHY IP. The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR2 SDRAM functionality 

Design Specifications

The table below lists the specifications for this design: 

Quartus versionQuartusII v9.1
KitArria II GX Development Kit
Memory deviceDDR2 SDRAM (Micron MT8HTF12864HDY-800G1 )
Memory speed333MHz
Memory topologyx64-bit, 667-Mbps DDR2 SODIMM
IP usedDDR2 SDRAM High Performance Controller II with ALTMEMPHY IP and generated example top Quartus project

Lab Steps

The lab uses Quartus II v9.1 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

Four files have been pre-designed for this lab to save time.

  • A pin location assignments tcl script (ArriaIIGX_DDR2_PinLocations.tcl)

  • A signal tap file for debug of the interface design that has been created

  • A board trace model assignments script (ArriaIIGX_DDR2_BTModels.tcl)

  • A virtual pins assignments script for this design (ArriaIIGX_DDR2_exdriver_vpin.tcl)

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file – 

Create a new folder for the project and place the files in it 


Design Generation

1. Use the Megawizard Plug-in Manager to generate a DDR2 SDRAM High Performance Controller 

Copy the memory parameters files, ArriaIIGX_DDR2_Kit(MT8HTF12864HDY-800G1).xml, to your <installation directory>\91\ip\ddr2_high_perf\lib directory.

Start Quartus, open MegaWizard Plug-In Manager and create a new variation.

  • In the Megawizard GUI, set device family to be Arria II GX 
  • The IP is located under the folders Interfaces/External Memory/DDR2 SDRAM, choose DDR2 SDRAM High Performance Controller v9.1
  • If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type 
  • For the name of the output file, browse to the folder you created above, give the instance the name “ddr2_sodimm”, click Open, click Next to open the IP GUI


2. Set parameters for Memory Controller with ALTMEMPHY

  • General Settings Tab 
  1. Set Speed grade to 5
  2. Set PLL reference clock frequency to 100 MHz.
  3. Set Memory clock frequency to 267 MHz
  4. For Memory Presets, select ArriaIIGX_DDR2_Kit(MT8HTF12864HDY-800G1), which gives a 64-bit wide, 800-Mbps 400-MHz
  5. Turn on the Enable Memory Chip Calibration in Timing Analysis option in the Advanced page of Memory Preset Editor. This option is required for Arria II GX devices, which need post-processing script to remove timing model pessimism
  • PHY Settings Tab
  1. Turn on Use differential DQS option under Advanced PHY
  2. Under Address/Command Clock Settings, for Dedicated clock phase type 90


  • Board Settings Tab
  1. Enter following values under Slew Rates:

               ■ CK/CK# slew rate (Differential) = 2.475 V/ns

              ■ Addr/Command slew rate = 0.859 V/ns

              ■ DQS/DQS# slew rate (Differential) = 1.386 V/ns

              ■ DQ slew rate = 2.665 V/ns

     2. Enter following values under Board Skews:

            ■ Max skew within DQS group = 0.0339 ns

            ■ Max skew between DQS groups = 0.0824 ns

             ■ Addr/Command to CK skew = 0.0356 ns

    3. The Intersymbol Interference parameters are not applicable for single rank configurations. Set all these parameters to 0 ns 

  • Controller Settings Tab

1. Set High Performance Controller II as Controller Architecture for higher efficiency and advanced features.

2. Under Efficiency, select the specified values for the following options:

   a. For Command Queue Look-Ahead Depth, select 6.

   b. For Local-to-Memory Address Mapping, select CHIP-ROW-BANK-COL.

   c. For Local Maximum Burst Count, select 8.

3. Click Next.

4. Turn the Generate simulation model option.Click “Finish” to start IP generation. Check important messages during generation. After IP is successfully generated, click Exit to close GUI. The ALTMEMPHY megafunction is instantiated automatically.


3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware.

  • Open the top-level entity file, <variation_name>_example_top.v or vhd
  • On the Project menu click Set as Top-Level Entity

4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the ALTMEMPHY for when the I/O assignments are created in the next step.

5. Set Optimization Technique

This step is required to ensure the remaining unconstrained paths are routed with the highest speed and efficiency. To set the optimization technique, perform the following steps:

  • On the Assignments menu, click Settings
  • Select Analysis & Synthesis Settings
  • Select Speed under Optimization Technique. Click OK

6. Set Fitter Effort

To set the fitter effort, perform the following steps:

  • On the Assignments menu, click Settings
  • Select Fitter Settings
  • Turn on Optimize hold timing and select All Paths
  • Turn on Optimize multi-corner timing
  • Select Standard Fit (highest effort) under Fitter effort
  • Click OK

7. Add Timing Constraints 

To add timing constraints, perform the following steps:

  • On the Assignments menu click Settings.
  • In the Category list, expand Timing Analysis Settings, and select TimeQuest
  • Timing Analyzer.
  • Select the <variation_name>_phy_ddr_timing.sdc file and click Add.
  • Click OK.

8. Assign the pin and DQ group settings 

Run the tcl script <variable_name>_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard

  • Verify in the Assignment Editor that pin assignments have been created successfully

9. Assign the pin locations 

Pin locations for external memory systems are not automatically created.

  • Run the ArriaIIGX_DDR2_PinLocations.tcl script to assign pin locations for the targeted kit
  • Run the ArriaIIGX_DDR2_exdriver_vpin.tcl script to assign virtual pins
  • Verify in Pin Planner or Assignment Editor that pin locations have been created successfully

10. Assign I/O Standards

To assign the I/O standards, perform the following steps:

  • On the Assignments menu, click Assignment Editor.
  • Specify LVDS as the I/O standard for clock_source.
  • Specify 1.8 V as the I/O standard for global_reset_n.

11. Enter board trace models

  • Run the ArriaIIGX_DDR2_BTModels.tcl script to enter the board trace model for the targeted kit

12. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

Design Analysis

1. Timing Analysis results

  • In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design. 

2. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation

  • Program the kit FPGA with the .sof
  • Run Signal Tap Analysis
  • - Restart the driver

   - Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

   - Also check that calibration was successful and that the PLL is locked

Design Simulation
  • Run EDA RTL Simulation from Tools Menu – Run EDA Simulation Tool -> EDA RTL Simulation

  - The simulation will stop once the test complete signal goes high in the test bench

  - CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset

  - Observe the results in the ModelSim Wave window



For a list of supported and unsupported features in the DDR2 SDRAM Controller with ALTMEMPHY, refer to the Altera's External Memory Interface Handbook. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Update History

Initial Release – January 2010 – Arria II GX DDR2 SDRAM x64 267MHz, Quartus II v9.1, DDR2 SDRAM High Performance Controller II with ALTMEMPHY, Arria II GX Development Kit.

See Also

1. List of designs using Altera External Memory IP 

External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

Version history
Last update:
‎06-25-2019 11:18 PM
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