Design Example – Arria V Hard Memory Controller DDR3 SDRAM UniPHY 533MHz x32

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Design Example – Arria V Hard Memory Controller DDR3 SDRAM UniPHY 533MHz x32

Contents

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• 1 Last Major Update
• 2 Design Overview
• 3 Design Specifications
• 4 Lab Steps
• 5 Design Generation
• 6 Design Analysis
• 7 Design Simulation
• 8 Notes/Comments
• 9 Update History
• 10 See Also
• 11 External Links
• 12 Key Words

Last Major Update

Initial Release – July 2012 – Arria V DDR3 SDRAM x32 533 MHz, Quartus II v12.0sp1, DDR3 SDRAM Controller with UniPHY.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 32-bit wide, 533-MHz DDR3 SDRAM hard memory interface working with a Arria V FPGA using a 32-bit wide DDR3 SDRAM interface comprises two MT41J64M16LA-15E DDR3 SDRAM components. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more thorough walkthrough. 

The UniPHY IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.

Design Specifications

The table below lists the specifications for this design:

Attribute	Specification
Quartus version	QuartusII v12.0sp1
FPGA	5AGXFB3H4F35C5ES
Kit	Arria V GX FPGA Development Kit
Memory device	DDR3 SDRAM (Micron MT41J64M16LA-15E)
Memory speed	533 MHz
Memory topology	X32-bit,2 DDR3 SDRAM components with T-topology
IP used	DDR3 SDRAM Controller with UniPHY IP and generated example top Quartus project

Lab Steps

The lab uses Quartus II v12.0sp1 and has Modelsim set up for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

Two files have been pre-designed for this lab to save time.

• A pin location assignments tcl script (a5gx_starter_pin_assignment.tcl)

• A signal tap file for debug of the interface design that has been created(stp1.stp)

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file – emi_uniphy_ddr3_av. 

Create a new folder for the project and place the files in it.

Design Generation

1. Use the Megawizard Plug-in Manager to generate a DDR3 SDRAM Controller with UniPHY

Start Quartus, open MegaWizard Plug-In Manager and create a new variation 

• In the Megawizard GUI, set device family to be Arria V 

• The IP is located under the folders Interfaces/External Memory/DDR3 SDRAM, choose DDR3 SDRAM Controller with UniPHY v12.0

• If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type 

• For the name of the output file, browse to the folder you created above, give the instance the name “ddr3x32_hard”, click Open, click Next to open the IP GUI

2. Set parameters for Memory Controller with UniPHY

Under Interface Type, turn on Enable Hard External Memory Interface option

• PHY Settings Tab

1. SetSpeed grade to 5.

2. Set Memory clock frequency to 533 MHz

3. Set PLL reference clock frequency to 100 MHz.

4. Select Full for Full- or half-rate Avalon-MM interface.

• Memory Parameters Tab

1. Select Micron for Memory vendor.

2. Select666.667 MHz for Memory device speed grade

3. Type 32 for Total interface width.

4. Select 1 for Number of slots and Number of chip selects

5. Select1 for Number of clocks.

6. Type 13 for Row address width.

7. Type 10 for Column address width.

8. Type 3 for Bank address width.

9. Select 7 for Memory CAS latency setting under Memory Initialization Options, 

10. Select RZQ/6 for Output drive strength setting.

11. Select 6 for Memory write CAS latency setting.

12. Select Dynamic ODT off for Dynamic ODT(Rtt_WR) setting. 

• Board Settings Tab 

1. Users should do board simulation for proper values in this page:

- In the Board Settings tab, set the slew rate parameters to the specified values below:

Slew Rate	Value (V/ns)
CK/CK# slew rate (Differential)	4.349
Address and command slew rate	2.174
DQS/DQS# slew rate (Differential)	4.349
DQ slew rate	2.174

- Set the Board Skews parameters to the specified values below:

Board Skews	Value (ns)
Maximum CK delay to DIMM/device	0.42
Maximum DQS delay to DIMM/device	0.437
Minimum delay difference between CK and DQS	0.0039
Maximum delay difference between CK and DQS	0.012
Maximum skew within DQS group	0.011
Maximum skew between DQS groups	0.029
Average delay difference between Address/Command and CK	-0.004
Average delay difference between DQ and DQS	0.039
Maximum skew within Address/Command bus	-0.001

• Controller Settings Tab 

Set 4 for Maximum Avalon-MM burst length under Avalon Interface

3. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware. 

• Open the example project located in <variation_name>_example_design/example_project. If the device you are using does not match the device in the example project, change the device in the project.

4. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.

5. Assign the pin and DQ group settings 

Run the tcl script ddr3x32_hard_example_if0_p0_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

• Verify in the Assignment Editor that pin assignments have been created successfully

6. Assign the pin locations 

Pin locations for external memory systems are not automatically created. 

• Run the a5gx_starter_pin_assignment.tcl script to assign pin locations for the targeted kit 

• Verify in Pin Planner or Assignment Editor that pin locations have been created successfully

7. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.

Design Analysis

1. Timing Analysis results 

• In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.

Design Simulation

The Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. To run the RTL simulation, perform the following steps:

• Open the generated example project for the design example simulation, <variation_name>_example_design/simulation generate_sim_example_design .qpf 

• Select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl or generate_sim_vhdl_example_design.tcl and click "Run". 

• Open Modelsim. 

• Move into the directory ./verilog/mentor or ./vhdl/mentor.

• Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

• The simulation will stop once the test complete signal goes high in the test bench 

• CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset 

• Observe the results in the ModelSim Wave window 

Notes/Comments

Update History

Initial Release – July 2012 – Arria V DDR3 SDRAM x32 533 MHz, Quartus II v12.0sp1, DDR3 SDRAM Controller with UniPHY, Arria V GX FPGA Development Kit

See Also

1. List of designs using Altera External Memory IP

External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

Key Words

UniPHY, DDR3 SDRAM, Design Example, External Memory , Arria V, Hard Memory Controller