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Design Example - Basic DDR3 UniPHY bring up

Design Example - Basic DDR3 UniPHY bring up



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Last Major Update

Major Update - October 2012 - update for Quartus 12.1

 

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR3 interface working with a Stratix IV FPGA using a single component on the Stratix IV GX FPGA Development kit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. The External Memory Interface Handbook should be referenced for more details.

 

The lab creates a 16bit 533MHz DDR3 external memory PHY and controller using Altera’s DDR3 SDRAM Controller with UniPHY IP. The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 functionality


6/62/UniPHY_IP_Example_Top_Project_Structure.JPG ( UniPHY IP Example Top Project Structure.JPG - click here to view image )


Design Specifications

The table below lists the specifications for this design:  

AttributeSpecification
Quartus versionQuartusII v12.1
FPGAEP4SGX230KF40C2
KitStratix IV GX FPGA Development kit (DK-DEV-4SGX230N/C2)
Memory deviceDDR3 (Micron MT41J64M16LA-15E)
Memory speed533MHz
Memory topologysingle component, x16
IP usedUniPHY with HPCII and generated example top Quartus project

 


Lab Steps

The lab uses Quartus II v12.1 and Modelsim 10.0d for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

Two files have been pre-designed for this lab to save time. 

  • A pin location assignments tcl script
  • A signal tap file for debug of the interface design that has been created

A Quartus archive for the final project is also included for reference.

Files for this lab are located in this zip file - UniPHY_basic_bring_up_lab_FILES.zip

Put the tcl file and the signal tap file in the same folder as the example top project that will be created next.

Design Generation

1. Use the Megawizard Plug-in Manager to generate a DDR3 Controller with UniPHY

Start Quartus, open MegaWizard Plug-In Manager and create a new variation

  • In the Megawizard GUI, set device family to be Stratix IV
  • The IP is located under the folders Interfaces/External Memory/DDR3 SDRAM, choose DDR3 SDRAM Controller with UniPHY v12.1
  • If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type
  • For the name of the output file, browse to the folder you created above, give the instance the name “ddr3_x16”, click Open, click Next to open the IP GUI


2. Set parameters for Memory Controller with UniPHY

On the right of the GUI are some Memory Presets, click Micron MT41J64M16LA-15E and apply

  • PHY Settings Tab

- Set Speed Grade to 2

- Set Memory Clock Frequency to 533.333MHz

- Set PLL Reference Clock Frequency to 100MHz

- Tick the Advanced Clock Phase Control box. Set -30° for additional addr/cmd clock phase. This is required because skew between add/cmd and CK on this board needs a 240° phase shift instead of 270°

- Keep the rest of this tab unchanged

  • Memory Parameters Tab - These are loaded from the preset but some settings are board related

- For this board. Set ODT Rtt nominal value to be RZQ/4 under Mode register 1. This value was determined from board simulation

- Keep the rest of this tab unchanged

  • Memory Timing Tab - Again loaded from the preset, users should confim data is correct against the memory vendor datasheet
  • Board Settings Tab - Users should do board simulation for proper values in this page

- Use Altera’s default settings

- In board skew section enter 0.3ns for average delay difference between address and command and CK

  • Controller Settings Tab – Keep all default settings
  • Keep all the defaults on the Diagnostics tab
  • Click “Finish” to start IP generation. Check "Generate Example Design" when the option comes up and click Generate. Also review important messages during generation. After IP is successfully generated, click Exit to close GUI 


3. Open the example project generated by the Megawizard

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware.

  • In Quartus, open project <>/ddr3_x16_example_design/example_project/ddr3_x16_example.qpf 
  • In the same folder as this project, place the tcl script and signal tap file downloaded from the zip file provided above
  • Set the device to be EP4SGX230KF40C2 (use ES device if thats on your kit), and set default I/O standard to be 1.5V
  • Is the Settings GUI, go to Signal Tap II Logic Analyzer settings, enable signal tap and add the pre-designed signal tap file UniPHY_basic_bring_up_lab_SignalTap.stp 


4. Perform Analysis and Synthesis

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step


5. Assign the pin and DQ group settings

Run the tcl script ddr3_x16_pin_assignments.tcl to assign the pin, clock and DQ group assignments. This tcl script is generated for you by the IP megawizard

  • Verify in the Assignment Editor that pin assignments have been created successfully 
  •  

6. Assign the pin locations Pin locations for external memory systems are not automatically created. 

  • Run the UniPHY_basic_bring_up_lab_Pin_Locations.tcl script to assign pin locations for the targeted kit
  • Verify in Pin Planner or Assignment Editor that pin locations have been created successfully 

 

7. Add I/O standard assignment for the pin clock_source

This step is particular to the target kit and may not be required on other boards.

In the Assignment Editor add the following assignment for the differential clock source

To                   Assignment Name       Value           Enabled

pll_ref_clk         I/O Standard                  LVDS           Yes

 

8. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.


Design Analysis 

1. Timing Analysis results

  • In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder 

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design. 


 4/4e/UniPHY_Example_DDR3_Timing_Report_Image.jpg ( UniPHY Example DDR3 Timing Report Image.jpg - click here to view image )



2. On board debug with Signal Tap

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation

  • Program the kit FPGA with the .sof 
  • Run Signal Tap Analysis

- Press the kit RESET button (S2) to restart the driver

- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

- Also check that calibration was successful and that the PLL is locked  


b/b5/UniPHY_Example_Top_Project_Signal_Tap_Results_Image.jpg ( UniPHY Example Top Project Signal Tap Results Image.jpg - click here to view image )


 Design Simulation

To simulate the example design a script needs to be run to set up Modelsim with the appropriate libraries and files

  • Open the generate_sim_example_design.qpf Quartus project which is located in the folder <>/ddr3_x16_example_design/simulation
  • From the Tools Menu -> Tcl Scripts.... select the generate_sim_verilog_example_design.tcl and click Run
  • Open Modelsim and change directory to <>/ddr3_x16_example_design/simulation/verilog/mentor
  • To start simulation enter "do run.do"

- The simulation will stop once the test complete signal goes high in the test bench

- CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset

- Observe the results in the ModelSim Wave window

 

Notes/Comments



Update History

  1. Initial Release - November 2nd 2010 - SIV DDR3 x16 533MHz, QuartusII v10.1b141a (customer beta), UniPHY + HPCII, SIV GX FPGA development kit.
  2. Major Update - October 2012 - update for Quartus 12.1


 

See Also

  1.   List of designs using Altera External Memory IP

 

External Links

  1. Altera's External Memory Interface Solutions Center
  2. Altera's External Memory Interface Handbook

 

Key Words

UniPHY, HPCII, DDR3, Design Example, External Memory

 

 

  

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