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Major Update - October 2012 - update for Quartus 12.1
This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR3 interface working with a Stratix IV FPGA using a single component on the Stratix IV GX FPGA Development kit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process. The External Memory Interface Handbook should be referenced for more details.
The lab creates a 16bit 533MHz DDR3 external memory PHY and controller using Altera’s DDR3 SDRAM Controller with UniPHY IP. The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 functionality
The table below lists the specifications for this design:
|Quartus version||QuartusII v12.1|
|Kit||Stratix IV GX FPGA Development kit (DK-DEV-4SGX230N/C2)|
|Memory device||DDR3 (Micron MT41J64M16LA-15E)|
|Memory topology||single component, x16|
|IP used||UniPHY with HPCII and generated example top Quartus project|
The lab uses Quartus II v12.1 and Modelsim 10.0d for simulation. The lab assumes the reader is a competent user of these tools and many of their features.
Two files have been pre-designed for this lab to save time.
A Quartus archive for the final project is also included for reference.
Files for this lab are located in this zip file - UniPHY_basic_bring_up_lab_FILES.zip
Put the tcl file and the signal tap file in the same folder as the example top project that will be created next.
1. Use the Megawizard Plug-in Manager to generate a DDR3 Controller with UniPHY
Start Quartus, open MegaWizard Plug-In Manager and create a new variation
2. Set parameters for Memory Controller with UniPHY
On the right of the GUI are some Memory Presets, click Micron MT41J64M16LA-15E and apply
- Set Speed Grade to 2
- Set Memory Clock Frequency to 533.333MHz
- Set PLL Reference Clock Frequency to 100MHz
- Tick the Advanced Clock Phase Control box. Set -30° for additional addr/cmd clock phase. This is required because skew between add/cmd and CK on this board needs a 240° phase shift instead of 270°
- Keep the rest of this tab unchanged
- For this board. Set ODT Rtt nominal value to be RZQ/4 under Mode register 1. This value was determined from board simulation
- Keep the rest of this tab unchanged
- Use Altera’s default settings
- In board skew section enter 0.3ns for average delay difference between address and command and CK
3. Open the example project generated by the Megawizard
The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware.
4. Perform Analysis and Synthesis
This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step
5. Assign the pin and DQ group settings
Run the tcl script ddr3_x16_pin_assignments.tcl to assign the pin, clock and DQ group assignments. This tcl script is generated for you by the IP megawizard
6. Assign the pin locations Pin locations for external memory systems are not automatically created.
7. Add I/O standard assignment for the pin clock_source
This step is particular to the target kit and may not be required on other boards.
In the Assignment Editor add the following assignment for the differential clock source
To Assignment Name Value Enabled
pll_ref_clk I/O Standard LVDS Yes
8. Do a Full Compile
This should take about 10 minutes depending on the compiling PC.
1. Timing Analysis results
- Check the summary at the bottom of that report
- Check that all set up and hold timings pass
Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.
2. On board debug with Signal Tap
Open the Signal Tap file and reset the .sof file to the one just created with the full compilation
- Press the kit RESET button (S2) to restart the driver
- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.
- Also check that calibration was successful and that the PLL is locked
To simulate the example design a script needs to be run to set up Modelsim with the appropriate libraries and files
- The simulation will stop once the test complete signal goes high in the test bench
- CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset
- Observe the results in the ModelSim Wave window
UniPHY, HPCII, DDR3, Design Example, External Memory
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