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Design Example - CIII ALTMEMPHY DDR2 150MHz x8 - SOPC Builder

Design Example - CIII ALTMEMPHY DDR2 150MHz x8 - SOPC Builder

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Last Major Update

Initial Release - November 18th 2010 - CIII ALTMEMPHY DDR2 150MHz, QuartusII v9.1

Design Overview

This design demonstrates high-performance DDR2 SDRAM at 150 MHz with SOPC Builder integrated in a Cyclone® III FPGA Development Kit board.

This design includes a Synopsis design constraint (SDC) file for Cyclone III FPGA development kit board clock assignments (cycloneIII_3c120_generic.sdc), a Tcl file for pin location assignments for DDR2 devices, an interface on column I/Os, and an example Nios® II test program (DDR_TEST.c).

Design Specifications

Design files are located here.

The table below lists the specifications for this design:  

Quartus versionQuartusII v9.1
KitCyclone III FPGA Development Kit
Memory deviceDDR2
Memory speed150MHz
Memory topologyOne DDR2 SDRAM x8 interface



Update History

  1. Initial Release - November 18th 2010 - CIII ALTMEMPHY DDR2 150MHz, QuartusII v9.1

See Also

  1.   List of designs using Altera External Memory IP


External Links

  1. Altera's External Memory Interface Solutions Center
  2. Altera's External Memory Interface Handbook


Key Words

ALTMEMPHY, DDR2, Design Example, External Memory, Cyclone III, CIII, SOPC Builder, SOPC



© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

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Version history
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Last update:
‎06-25-2019 11:21 PM
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