cancel
Showing results for 
Search instead for 
Did you mean: 
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
831 Discussions

Design Example: Chip ID Reading using AVST Mailbox IP in Agilex

This design example shows the Chip IP reading functionality using AVST Mailbox IP in Agilex Development Kit. Chip ID reading functionality is implemented in Verilog and connection with AVST Mailbox IP is required to communicate with Flash Memory.

The design example may be found in the Intel FPGA Design Store at https://fpgacloud.intel.com/devstore/platform/2319/

The attached document "Chip ID Reading using AVST Mailbox IP in Agilex.pdf" provides more details on using the design example.

Attachments
Version history
Revision #:
4 of 4
Last update:
‎07-21-2020 05:09 PM
Updated by:
 
Contributors