1) Download and unzip the zip files linked above into a folder to be used as the download directory.
2) Open the project file (.qpf) by going to File > Open Project and navigating to <download_directory>\SV_Custom_PMA_Reconfig\source. Open top.qpf.
3) Use the Megawizard Plug-in Manager to generate Altera Generated IP
Before compiling you must regenerate the Altera generated IP using the Megawizard. You will perform this step twice - once for the top_custom.v and once for the top_reconfig.v. Open MegaWizard Plug-In Manager and choose edit a variation.
Select the IP you want to edit and generate (The .v file will be located in your project directory).
If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type (The default settings will work for this example).
Select the options for the IP you want to generate (The default settings will work for this example), and click Finish.
After the previous steps have been completed, you can compile the entire design by going to Processing > Start > Start Analysis and Synthesis.
4) During compilation you can expect following critical warnings
Critical Warning (18061): Ignored Power-Up Level option on the registers
Critical Warning: Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (169085): No exact pin location assignment(s) for 39 pins of 39 total pins.
Critical Warning: Timing requirements not met.
The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl