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Design Example - Custom PHY IP w/ PMA Controls Reconfiguration (Stratix V GX)

Design Example - Custom PHY IP w/ PMA Controls Reconfiguration (Stratix V GX)

External Links

Altera Transceiver PHY IP Core User Guide (PDF) 

Altera Stratix V Device Documentation

Altera Avalon Memory-Mapped Interface Specification (PDF)

 

 

Design File

for Quartus II v11.0 

Altera Stratix V Custom PHY IP PMA reconfiguration v11.0 (ZIP)

for QuartusII v13.1 

Altera Stratix V Custom PHY IP PMA reconfiguration v13.1 (ZIP)

Design Specifications

The table below lists the specifications for this design:  

Attribute Specification
Device Family Stratix V GX
FPGA 5SGXMA7K2F40C2
Quartus version QuartusII v11.0, b157
Modelsim version Modelsim SE v6.6d
Datarate 3.125Gbps
Data pattern PRBS 23
Number of channels
IP used Custom PHY IP, Traceiver Reconfiguration Controller

  

The table below lists the specifications for the design for v13.1:  

Attribute Specification
Device Family Stratix V GX
FPGA 5SGXMA7K2F40C2
Quartus version QuartusII v13.1 b162
Modelsim version Modelsim SE v10.0d
Datarate 3.125Gbps
Data pattern PRBS 23
Number of channels
IP used Custom PHY IP, Traceiver Reconfiguration Controller

 

Design Overview

This design implements the following blocks:

  1. Two Custom PHY IP instances
  2. One Transceiver Reconfiguration Controller
  3. PRBS Generator
  4. PRBS Checkers
  5. Avalon Memory-Mapped (MM) Masters
  6. Reconfiguration Controller Avalon Memory-Mapped (MM) Master

 

 

 

 

 

Compilation in Quartus 

1) Download and unzip the zip files linked above into a folder to be used as the download directory.

 

2) Open the project file (.qpf) by going to File > Open Project and navigating to <download_directory>\SV_Custom_PMA_Reconfig\source. Open top.qpf. 

 

3) Use the Megawizard Plug-in Manager to generate Altera Generated IP

Before compiling you must regenerate the Altera generated IP using the Megawizard. You will perform this step twice - once for the top_custom.v and once for the top_reconfig.v. Open MegaWizard Plug-In Manager and choose edit a variation. 

  • Select the IP you want to edit and generate (The .v file will be located in your project directory).
  • If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type (The default settings will work for this example). 
  • Select the options for the IP you want to generate (The default settings will work for this example), and click Finish. 

After the previous steps have been completed, you can compile the entire design by going to Processing > Start > Start Analysis and Synthesis. 

4) During compilation you can expect following critical warnings

  • Critical Warning (18061): Ignored Power-Up Level option on the registers
  • Critical Warning: Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • Critical Warning (169085): No exact pin location assignment(s) for 39 pins of 39 total pins.
  • Critical Warning: Timing requirements not met.

Simulation Guidelines

The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl

 

Update History

  1. Initial Release - May 16 2011 

 

 See Also

  1.  Transceiver design examples 

 

Key Words

Stratix V, Custom PHY IP, Tranceiver Reconfiguration Controller, PMA reconfiguration, dynamic reconfiguration, analog reconfiguration, transcevier reconfiguration, xcvr reconfiguration, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX

 

   

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supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.Retrieved from http://www.alterawiki.com/wiki/Altera_Wiki

 

Version history
Revision #:
2 of 2
Last update:
‎11-01-2020 03:26 PM
Updated by: