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Design Example - GIGE PHY IP (Stratix V GX)

Design Example - GIGE PHY IP (Stratix V GX)



External Links

Altera Transceiver PHY IP Core User Guide (PDF)

Altera Stratix V Device Documentation

Altera Avalon Memory-Mapped Interface Specification (PDF)


Design File

for Quartus II v11.0 

Altera GIGE Design File (ZIP)  

for Quartus II v13.1 

Altera GIGE Design File (ZIP)  


Note: v13.1 design file is created by regenerating all the megafunction files of the older Quartus version by selecting tools -> Megafunction Plug-In Manager -> Edit a custom megafunction variation -> next -> selecting 1 file at a time -> next -> check if all parameter values are same as older megafunction -> finish.


Design Specifications

The table below lists the specifications for the design with QuartusII version 11.0:  

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v11.0, b157
Modelsim versionModelsim SE v6.6d
Datarate1.25Gbps
Data patternCustom Test Pattern
Number of channels
IP usedGIGE PHY IP, Traceiver Reconfiguration Controller

  

The table below lists the specifications for the design with QuartusII version 13.1:  

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v13.1
Modelsim versionModelsim SE v10.0d
Datarate1.25Gbps
Data patternCustom Test Pattern
Number of channels
IP usedGIGE PHY IP, Traceiver Reconfiguration Controller

 

Design Overview

This design implements the following blocks:

  1. GIGE PHY IP
  2. Transceiver Reconfiguration Controller
  3. PRBS Generator
  4. PRBS Checker
  5. Avalon Memory-Mapped (MM) Master

b/bd/Gige_block.JPG ( Gige block.JPG - click here to view image )


Simulation Guidelines

The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl


Compilation in Quartus

  1. Open the project file (.qpf) by going to File > Open Project and navigating to <project_directory>\10GBASER_checkout_mif_A7. Open sv_gige.qpf.
  2. Before compiling you must regenerate the Altera generated IP using the Megawizard. Perform the following steps for however many altera generated IPs there are in the design. Go to Tools > Megawizard Plugin Manager. Once the dialogue box opens up, select "edit an exisitng custom megafunction variation." select the file you want to generate (there will be several .v files to choose from, and you will need to complete this process for each of them). Then click next. After a few moments another dialogue box will appear. Here you will be able to customize the Altera generated IP. After you have selected your options, click Finish and the file will be generated.
  3. After the previous steps have been completed, you can compile the entire design by going to Processing > Start Compilation.
  4. You can expect following critical warnings during compilation.
  • No exact pin location assignment(s) for 83 pins of 83 total pins
  • Synopsys Design Constraints File file not found: 'sv_gige.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • Timing requirements not met.



Key Words

Stratix V, GIGE PHY IP, Tranceiver Reconfiguration Controller 

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Revision #:
1 of 1
Last update:
‎06-27-2019 12:41 AM
Updated by:
 
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