Note: v13.1 design file is created by regenerating all the megafunction files of the older Quartus version by selecting tools -> Megafunction Plug-In Manager -> Edit a custom megafunction variation -> next -> selecting 1 file at a time -> next -> check if all parameter values are same as older megafunction -> finish.
The table below lists the specifications for the design with QuartusII version 11.0:
Stratix V GX
QuartusII v11.0, b157
Modelsim SE v6.6d
Custom Test Pattern
Number of channels
GIGE PHY IP, Traceiver Reconfiguration Controller
The table below lists the specifications for the design with QuartusII version 13.1:
The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl
Compilation in Quartus
Open the project file (.qpf) by going to File > Open Project and navigating to <project_directory>\10GBASER_checkout_mif_A7. Open sv_gige.qpf.
Before compiling you must regenerate the Altera generated IP using the Megawizard. Perform the following steps for however many altera generated IPs there are in the design. Go to Tools > Megawizard Plugin Manager. Once the dialogue box opens up, select "edit an exisitng custom megafunction variation." select the file you want to generate (there will be several .v files to choose from, and you will need to complete this process for each of them). Then click next. After a few moments another dialogue box will appear. Here you will be able to customize the Altera generated IP. After you have selected your options, click Finish and the file will be generated.
After the previous steps have been completed, you can compile the entire design by going to Processing > Start Compilation.
You can expect following critical warnings during compilation.
No exact pin location assignment(s) for 83 pins of 83 total pins
Synopsys Design Constraints File file not found: 'sv_gige.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.