Community
cancel
Showing results for 
Search instead for 
Did you mean: 

Design Example - Interlaken

Design Example - Interlaken



External Links

Altera Transceiver PHY IP Core User Guide (PDF) 

Altera Stratix V Device Documentation

Altera Avalon Memory-Mapped Interface Specification (PDF)


Design File

Altera Interlaken Design File (ZIP)  (Quartus II v11.0 build 157 compatible)

Altera Interlaken Design File (ZIP)  (Quartus II v12.1 build 177 compatible or Quartus II v13.1 build 162 compatible)


Design Specifications

The table below lists the specifications for the Quartus II version 11.0 build 157 design:  

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v11.0, b157
Modelsim versionModelsim SE v6.6d
Datarate6.25Gbps
Data patternPRBS 23
Number of channels1
IP usedInterlaken PHY IP, Transceiver Reconfiguration Controller


The table below lists the specifications for the Quartus II version 12.1 build 177 design or Quartus II version 13.1 build 162 compatible:

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v12.1, b177 or QuartusII v13.1, b162
Modelsim versionModelsim Altera Starter Edition v10.1b
Datarate6.25Gbps
Data patternPRBS 23
Number of channels1
IP usedInterlaken PHY IP, Transceiver Reconfiguration Controller













.




Design Overview

This design implements the following blocks:

  • top_interlaken_phy (User Generated)
  • interlaken_phy  (Altera Generated)
  • top_reconfig (Altera Generated)
  • reset (User Generated)
  • mgmt_master (User Generated)
  • prbs_generator (User Generated)  
  • prbs_checker (User Generated)
  • frequency_checker (User Generated)


6/64/Interlaken_top_level_schematic.png ( Interlaken top level schematic.png - click here to view )


Compilation in Quartus 

1) Download and unzip the zip files linked above into a folder to be used as the download directory.


2) Open the project file (.qpf) by going to File > Open Project and navigating to <download_directory>\Interlaken_PHY\source. Open top.qpf. 


3) Use the Megawizard Plug-in Manager to generate Altera Generated IP (labeled in figure 1-1)

Before compiling you must regenerate the Altera generated IP using the Megawizard. You will perform this step twice - once for the top_custom.v and once for the top_reconfig.v. Open MegaWizard Plug-In Manager and choose edit a variation. 

  • Select the IP you want to edit and generate (The .v file will be located in your project directory).
  • If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type (The default settings will work for this example). 
  • Select the options for the IP you want to generate (The default settings will work for this example), and click Finish. 

After the previous steps have been completed, you can compile the entire design by going to Processing > Start > Start Analysis and Synthesis. 

4) During compilation you can expect following critical warnings

  • Critical Warning (169085): No exact pin location assignment(s) for 22 pins of 22 total pins.
  • Critical Warning: Timing requirements not met.



Simulation Guidelines

The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl



Update History

  1. Initial Release - May 05 2011 
  2. Updated Block Diagram & Design Files - December 18 2012 


See Also

  1. Transceiver design examples 

 

Key Words

Stratix V, Interlaken PHY IP, Tranceiver Reconfiguration Controller, S, V, StratixV, GT, GX, Quartus II, 12.0


Disclaimer

© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.Retrieved from http://www.alterawiki.com/wiki/Altera_Wiki

Version history
Revision #:
1 of 1
Last update:
‎06-25-2019 11:24 PM
Updated by:
 
Contributors