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Design Example - Modular PCIe SOPC Builder Bridge

Design Example - Modular PCIe SOPC Builder Bridge



Last Updated

August 16, 2011


Description

This Modular PCIe SOPC Builder Bridge example has been created to illustrate how one might go about implementing a bridge from the Altera PCIe core’s Avalon ST interfaces into the Avalon MM domain of SOPC Builder. The Altera PCIe core implements a bridge similar to this in the standard component, however for some application requirements the capabilities of the standard PCIe SOPC Builder bridge are inadequate. Some of the limitations of the standard PCIe SOPC Builder bridge that this Modular PCIe SOPC Builder Bridge example addresses are higher performance modes of the PCIe core, root port capability, and multiple MSI support. The current implementation of the standard PCIe SOPC Builder bridge can only support PCIe modes that operate up to 125MHz over a 64-bit data path, so Gen1x4 represents the highest performance that the data path of the standard bridge will support. The current standard bridge has no support for root port operation and it only supports 1 MSI and only 16 TAGs. All of these limitations are addressed in the Modular PCIe SOPC Builder Example and in theory the only limitations of the Modular bridge are those limitations that are imposed by the Altera PCIe core’s Avalon ST capabilities. The current Modular PCIe SOPC Builder Bridge components are limited to PCIe modes that run over the 64-bit Avalon ST data path, but they can run up to 250MHz, which means that Gen1x8 and Gen2x4 architectures can be implemented. The modular bridge example also supports root port operation, 32 MSIs, and 64 TAGs, which are the current limitations imposed by the Altera PCIe Avalon ST implementation.

 

 a/a0/Modular_pcie_concept_image.jpg ( Modular pcie concept image.jpg - click here to view image )


Contents

The archive that is distributed for this example contains some limited PDF documentation that illustrates the concept and usage of the Modular PCIe SOPC Builder Bridge along with archives of all the custom components that were created to architect the bridge, as well as a number of example designs that illustrate various uses of the bridge like typical endpoint and root port implementations and more. The archive also contains a number of the verification systems that were used during development to test the functionality of the bridge architecture as well as the Fmax performance of various bridge components. There are readme.txt files located in almost every subdirectory in the archive which should provide additional information about the contents of each directory and their purpose.


Instructions

Downloading the examples

Download the archives you are interested in and place them in a directory on your system that does not include spaces in the path name. The entire path name of this directory must not contain spaces, so on Windows systems you should avoid putting these in the "My Documents" folder, or on your "Desktop" since these locations are subdirectories of the "Documents and Settings" path, and that would mean that these locations inherit the spaces in that part of the path name.

In order to extract the archives after downloading them, it is recommended that you run the "tar xzf <filename>" command from a bash shell. For linux users you should have ready access to a bash shell. For windows users, you may need to install the Altera development tools to gain access to a bash shell. On Windows it is recommended that you install the Altera Quartus II FPGA development tools along with the IP base suite as well as the Nios II EDS development tools, and if you do not have a version of ModelSim you should install the ModelSim ASE tools. Once these tool chains are properly installed on your workstation, you can launch a bash shell by running:

"Start -> Programs -> Altera -> Nios II EDS X.x -> Nios II X.x Command Shell"

Once you are in the bash shell, you can "cd" into the directory containing the archives that you've downloaded, and run the following command to extract them:

tar xzf <archive_filename>

Note that if you use some other archiving software to extract these archives, like WinZip, you may lose the execution privileges on some of the shell scripts within the archives that are used to perform various activities associated with building and using the example. If this happens, you can restore execute privileges from within a bash shell with the command "chmod +x <filename>". It is recommended that you avoid this situation by using "tar" to extract the archives from within a bash shell and avoid using any Windows oriented archive utilities with these archives.


Building the examples

After you have extracted the main archive you should be able to locate additional archives and readme files within it. The latest_stable_components archive directory is generally required by all of the other examples and tests provided with the example, so you should probably extract that archive within the top level of the example directory. From here you can search thru the rest of the material provided in the example and read the readme explanations. In general if you want to try one of the examples out, it should be as easy as extracting that specific archive and then running the build script located within the extracted directory. The build scripts are bash shell scripts so run them from the command line similar to how you ran the tar utility to extract them. For information about how the examples are built, please refer to the build scripts, these are text files that you can read and they essentially document the sequence of events used to construct the example project. Once you have built an example, you can examine the resultant Quartus project for information about how the system was constructed and any other details about the SOPC system and Quartus project.



Requirements

This 20110816 release has been tested on the Altera ACDS 9.1 platform. All tests, build scripts, etc should work just fine in the 9.1 environment assuming that you have Quartus II, IP Suite, Nios II EDS and ModelSim ASE installed and operational.

Some minimal testing has been done under 10.0, however, due to a difference in the way that SOPC Builder generates the top level SOPC file, some editing of the include files is required to allow the simulation tests to function properly. The current build scripts do not perform this alteration, so you will not have much success building the simulation projects from the provided build scripts. Once you get past this minor discrepancy in 10.0, the components, the bridge and all of the tests provided within this example do appear to function properly.



See Also

Altera PCI Express Compiler User Guide

Altera Online Demonstration of PCI Express Compiler

Altera PCI Express Hard IP



Update History

20110816 - Bug fix applied to completion_generator_64b_piped, see the change_log in latest_stable_components for details.

20110502 - Bug fix applied to pcie_tlp_classify_64b, see the change_log in latest_stable_components for details. Also added component pcie_cfg0_conditioner_64b, also detailed in change_log and readme.txt.

20110219 - Bug fix applied to completion_generator_64b and completion_generator_64b_piped, see the change_log.txt in latest_stable_components for details. Also added component null_tlp_src_64b.

20100902 - Initial posting.



Outdated Releases

20110502_modular_pcie_bridge.tgz

20110217_modular_pcie_bridge.tgz 

20100901_modular_pcie_bridge.tgz


Root Port Implementations

The pcie_cfg0_conditioner_64b component was added to the latest_stable_components archive in the 20110502 release to address an issue that arises in root port PCIe HIP implementations which was previously posted to this wiki page as an errata. The previously posted errata was actually a documented requirement that is now covered in later versions of the PCIe compiler core user guide. This pcie_cfg0_conditioner_64b component is intended to implement the required transfer pause required by the PCIe HIP core after a CFG0 packet is sent into the core. The PCIe User Guide states that you must wait for the TX FIFO to empty and allow the configuration space transaction to complete before allowing additional TLP packets to enter the PCIe HIP. This only affects root port implementations of the PCIe HIP. This pcie_cfg0_conditioner_64b appears to adequately satisfy the requirements of the HIP root port implementations, and should be placed in front of the PCIe HIP TX sink interface for all egressing packets to flow through. There are currently no examples included to demonstrate the use of this component in the bridge, but it has been functionally tested in Stratix IV.

© 2011 Altera Corporation.

The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own

risk; it might be, for example, objectionable, misleading or inaccurate.

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